公开(公告)号：US20110018608A1

公开(公告)日：2011-01-27

申请号：US12842903

申请日：2010-07-23

申请人： Min-hwa Chi ,  Lihying Ching ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Lihying Ching ,  Deyuan Xiao

IPC分类号： H03K17/60 ,  H01L21/331 ,  H01L29/70 ,  G05F1/10

CPC分类号： H01L29/66325 ,  G05F3/30 ,  H01L21/26586 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7393 ,  H03K17/60

摘要： The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact.

摘要翻译： 本发明提供一种双极晶体管，双极型晶体管的形成方法，双极型晶体管的导通方法，带隙基准电路，虚拟接地参考电路以及双极性晶体管的双带隙基准电路。 双极晶体管包括：绝缘体上硅晶片; 基极区域，发射极区域和集电极区域; 位于顶部硅层上的基极区电介质层，并在基底区域顶部; 基区栅极电介质层上的基区控制栅极; 经由第一触点连接到发射极区域的发射极; 集电极，经由第二触点连接到集电区; 以及通过第三触点连接到基区控制门的基区控制栅电极。 形成双极晶体管的工艺与传统的标准CMOS工艺完全兼容; 并且用于导通双极晶体管的基极电流基于GIDL电流并且通过向基极区域控制栅电极施加电压而形成，而不需要接触。

公开(公告)号：US07078766B2

公开(公告)日：2006-07-18

申请号：US09865929

申请日：2001-05-24

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L27/11 ,  H01L29/78612

摘要： A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the VCC and VSS. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.

公开(公告)号：US06552397B1

公开(公告)日：2003-04-22

申请号：US09602401

申请日：2000-06-23

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L2972

CPC分类号： H01L27/1203 ,  G11C5/145 ,  H02M3/073

摘要： A charge pump formed in a silicon-on-insulator (SOI) substrate is disclosed. The charge pump comprises a SOI layer formed on a substrate. Formed in the silicon of the SOI is a first p-body and a second p-body. Also formed in the silicon is a n+ region that extends down to the insulator so that the n+ region separates the first p-body and second p-body. Finally, a gate structure is formed atop of a portion of the first p-body and a portion of the n+ region. The gate structure is separated from the 1st p-body and n+ region by gate oxide, and it serves as charge pump capacitor. Both the diode turn-on (when gate is pulsing high and forward biasing the p-body to n+ junction), and GIDL current (when the gate is pulsing low, and generates GIDL hole currents from n+ surface to p-body) will result in a “short” of the p-body and n+ region; this ensures the proper operation of charge pump.

摘要翻译： 公开了一种形成在绝缘体上硅（SOI）衬底中的电荷泵。 电荷泵包括在衬底上形成的SOI层。 在SOI的硅中形成的是第一个p体和第二个p体。 在硅中还形成有向下延伸到绝缘体的n +区域，使得n +区域分离第一p体和第二p体。 最后，栅极结构形成在第一p体的一部分和n +区的一部分的顶部。 栅极结构通过栅极氧化物与第一p体和n +区分离，并且其用作电荷泵电容器。 二极管导通（当门脉冲高且正向偏压p体至n +结时）和GIDL电流（当栅极脉冲低，并从n +表面到p体产生GIDL空穴电流时）将导致 在p体和n +区域的“短”中; 这样可确保电荷泵的正常运行。

公开(公告)号：US06240015B1

公开(公告)日：2001-05-29

申请号：US09545038

申请日：2000-04-07

申请人： Min-hwa Chi ,  Dahcheng Lin

发明人： Min-hwa Chi ,  Dahcheng Lin

IPC分类号： G11C1600

CPC分类号： G11C16/26 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C2211/565

摘要： A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.

摘要翻译： 公开了一种读取具有漏极，源极，控制栅极和浮置栅极的2位存储单元的方法。 首先，向源极和漏极施加电压以产生栅极感应漏极泄漏（GIDL）电流。 接下来，测量所述漏极处的漏极GIDL电流和在所述源极处的源极GIDL电流，以确定存储在所述存储器单元中的数据。

公开(公告)号：US06174770B1

公开(公告)日：2001-01-16

申请号：US09419402

申请日：1999-10-14

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

摘要： A method for manufacturing a semiconductor capacitor atop a conductive plug that is formed in a dielectric layer. A first oxide layer is formed on the dielectric layer and the conductive plug. Next, a crown opening in formed in the first oxide layer such that the conductive plug is exposed. Silicon sidewall spacers are formed on the sidewalls of the crown opening and then HSG silicon is formed on the silicon sidewall spacers. The HSG silicon and silicon sidewall spacers are oxidized and then a doped polysilicon layer is formed into the aid crown opening and over the oxidized HSG silicon. A thin dielectric layer is formed over the aid doped polysilicon layer and finally a top conductive layer is formed over the thin dielectric layer.

摘要翻译： 一种用于在形成在电介质层中的导电插塞顶上制造半导体电容器的方法。 在介电层和导电插塞上形成第一氧化物层。 接下来，形成在第一氧化物层中的导电插头露出的冠状开口。 在胎冠开口的侧壁上形成硅侧壁间隔物，然后在硅侧壁间隔件上形成HSG硅。 HSG硅和硅侧壁间隔物被氧化，然后将掺杂的多晶硅层形成为辅助冠开口和氧化的HSG硅上。 在辅助掺杂多晶硅层上形成薄介电层，最后在薄介电层上形成顶部导电层。

公开(公告)号：US6163482A

公开(公告)日：2000-12-19

申请号：US378558

申请日：1999-08-19

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C11/22 ,  G11C16/04 ,  H01L29/78

CPC分类号： G11C11/22 ,  G11C16/04 ,  H01L29/78391

摘要： A new one-transistor EEPROM cell structure using a spacer of ferro-electric material (e.g. PZT or BST). The spacer's polarization can be alterable and is used as the storage element of digital information. This new cell offers small cell size, low voltage operation, high endurance, fast write operation, and full function EEPROM compared to conventional EEPROM or F-RAMS.

摘要翻译： 使用铁电材料（例如PZT或BST）的间隔件的新的单晶体管EEPROM单元结构。 间隔物的极化可以是可变的，并且被用作数字信息的存储元件。 与常规EEPROM或F-RAMS相比，这个新单元提供小单元尺寸，低电压操作，高耐久性，快速写操作和全功能EEPROM。

公开(公告)号：US6133780A

公开(公告)日：2000-10-17

申请号：US326166

申请日：1999-06-04

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G05F3/30 ,  G05F1/10 ,  G05F3/02

CPC分类号： G05F3/30

摘要： A digitally tunable voltage reference circuit based on floating gate neuron MOSFETs and a V.sub.t referenced voltage source configuration is disclosed. The voltage reference can provide a wide range of voltage levels by biasing digital signals to the multiple inputs of the neuron MOSFET in the voltage source.

摘要翻译： 公开了一种基于浮栅神经元MOSFET的数字可调电压参考电路和Vt参考电压源配置。 电压参考可以通过将数字信号偏置到电压源中的神经元MOSFET的多个输入端来提供宽范围的电压电平。

公开(公告)号：US6111286A

公开(公告)日：2000-08-29

申请号：US177786

申请日：1998-10-22

申请人： Min-hwa Chi ,  Chih Ming Chen

发明人： Min-hwa Chi ,  Chih Ming Chen

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7883

摘要： A flash memory cell formed on a semiconductor substrate is disclosed. The cell comprises: a p-well formed in the substrate; a gate structure formed atop the p-well, the gate structure including a control gate and a floating gate, the floating gate electrically isolated from the control gate and the semiconductor substrate by a thin dielectric layer; an n- base formed adjacent to a first edge of the gate structure and extending underneath the gate structure; a p+ structure formed within the n- base and adjacent to the first edge of the gate structure; and a n+ structure adjacent a second edge of the gate structure. With such a structure, it is possible to program the cell by band-to-band tunneling enhanced hot electrons generated at the p+ surface. The erase is performed by Fowler-Nordheim tunneling through the n- base region.

摘要翻译： 公开了一种形成在半导体衬底上的闪存单元。 该电池包括：在衬底中形成的p阱; 栅极结构形成在p阱的顶部，栅极结构包括控制栅极和浮置栅极，通过薄介电层与控制栅极和半导体衬底电隔离的浮置栅极; 形成在栅极结构的第一边缘附近并在栅极结构下方延伸的n-基极; 形成在所述n基极内且与所述栅极结构的第一边缘相邻的p +结构; 以及与栅极结构的第二边缘相邻的n +结构。 通过这样的结构，可以通过在p +表面产生的带对带隧穿增强的热电子对单元进行编程。 擦除由Fowler-Nordheim穿过n基区进行。

公开(公告)号：US06088259A

公开(公告)日：2000-07-11

申请号：US253322

申请日：1999-02-19

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C11/412 ,  G11C11/00

CPC分类号： G11C11/412

摘要： A SRAM cell is disclosed. The SRAM cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, the output of the second inverter capacitively coupled to the input of the first inverter, the input of the second inverter capacitively coupled to the output of the first inverter; a first access transistor controlled by a wordline and connected between the output of the first inverter and a bitline; and a second access transistor controlled by the wordline and connected between the output of the second inverter and a complement to the bitline.

摘要翻译： 公开了一种SRAM单元。 SRAM单元包括：具有输入和输出的第一反相器; 具有输入和输出的第二反相器，与第一反相器的输入电容耦合的第二反相器的输出，与第一反相器的输出电容耦合的第二反相器的输入; 由字线控制并连接在第一反相器的输出端和位线之间的第一存取晶体管; 以及由字线控制并连接在第二反相器的输出和位线的补码之间的第二存取晶体管。

公开(公告)号：US6087690A

公开(公告)日：2000-07-11

申请号：US170863

申请日：1998-10-13

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/108

摘要： A single polysilicon DRAM cell is disclosed. The DRAM cell comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well, the gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n+ well within the p-well and adjacent to a sidewall of the gate structure. The p-well potential can be reset to -V.sub.cc /2 representing "0", and written to V.sub.cc /2 representing "1". The parasitic n-channel MOS with the p-well as the "body" will have a threshold voltage modulated by the p-well potential at V.sub.cc /2 and -V.sub.cc /2 for representing "1" and "0" states, respectively.

摘要翻译： 公开了单个多晶硅DRAM单元。 DRAM单元包括：硅衬底中的深n阱; 深井内的p井; 栅极结构在其上并跨越深n阱和p阱，栅极结构是薄栅极氧化物层和导电层的堆叠; 和p阱内的n +阱并且与栅极结构的侧壁相邻。 p阱电位可以复位为-Vcc / 2，表示“0”，并写入表示“1”的Vcc / 2。 具有p阱作为“体”的寄生n沟道MOS将分别由Vcc / 2和pcc阱的p阱电位调制阈值电压，并分别表示“1”和“0”状态。