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41.发明授权Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output 失效可编程偏移时钟信号发生器响应于相位累加器输出选择多个延迟参考时钟信号中的一个公开(公告)号：US06959397B2
公开(公告)日：2005-10-25
申请号：US10464239
申请日：2003-06-18
CPC分类号： H03L7/0812 , G06F1/06
摘要： A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal Fφ0 from a reference signal Fref A frequency accumulator (132, 152) is preloaded with a preload value PK1 and receives one reference signal cycle as a clock signal, receives a constant K1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1 as an input thereto. The phase accumulator (136, 156) has a maximum count CMAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Fref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fφ1 whose phase shift φ1 relative to F0φ is a function of PK1 and PC1.
摘要翻译： 可编程偏移时钟信号发生器具有与本发明一致的频率发生器电路（104），从参考信号F REF（频率累加器）132产生一个输出信号F < 152）预加载有预载值P SUB K1并且接收一个参考信号周期作为时钟信号，接收常数K 1作为其输入，与频率累加器（ 132，152）具有最大计数K MAX，并产生溢出输出。 相位累加器（136,156）预加载有预载值P SUB C1，并且从频率累加器（132,152）输出的一个溢出周期作为时钟信号，并接收相位偏移常数C < SUB> 1 作为其输入。 相位累加器（136,156）具有最大计数C MAX，并产生相位累加器（136,156）的输出。 延迟线（320）由参考信号F REF被定时并且在多个抽头输出处产生多个延迟的参考时钟信号。 抽头选择电路（140,144; 160,164）接收相位累加器输出，并响应于此选择抽头输出中的至少一个以产生其相移phi < 1 相对于F 0 是P＆lt; K1＆gt;和＆lt; C1＆gt;的功能。
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公开(公告)号：US06462360B1
公开(公告)日：2002-10-08
申请号：US09921901
申请日：2001-08-06
IPC分类号： H01L2128
CPC分类号： H01L27/0605 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02513 , H01L21/02521 , H01L21/8221 , H01L21/8258 , H01L27/0688 , H01L2924/00011 , H01L2224/80001
摘要： Composite semiconductor structures and methods are provided for communications systems, specifically, those utilizing RF signals. Antenna switches, and amplifiers in receiver and transmitter sections of the communications systems are shown that are fabricated within a compound semiconductor layer of a composite semiconductor structure is integrated with support circuitry in a non-compound semiconductor substrate. Support circuitry that may be integrated include negative voltage generation circuitry, drain current protection circuitry, and voltage regulation circuitry.
摘要翻译： 提供了用于通信系统的复合半导体结构和方法，特别是利用RF信号的那些。 示出了在通信系统的接收机和发射机部分中的天线开关和放大器，其在复合半导体结构的化合物半导体层内制造，与非化合物半导体衬底中的支持电路集成。 可以集成的支持电路包括负电压产生电路，漏极电流保护电路和电压调节电路。
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43.发明授权High efficiency power amplifier having reduced output matching networks for use in portable devices 有权具有减少的用于便携式设备的输出匹配网络的高效率功率放大器公开(公告)号：US06262629B1
公开(公告)日：2001-07-17
申请号：US09347675
申请日：1999-07-06
IPC分类号： H03F368
CPC分类号： H03F1/0288 , H03F1/0261 , H03F2200/198
摘要： A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier (208), and an impedance transforming network (214). The peaking amplifier path includes a peaking amplifier (210), an impedance transforming network (216), and a phase delay quarter wave element (226). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node (230) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal (232) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die (304). The impedance transforming networks and phase delay element are disposed on a common substrate (306), as is an input splitter network (308).
摘要翻译： 功率放大器包括载波放大器路径和峰化放大器路径。 载波放大器路径包括载波放大器（208）和阻抗变换网络（214）。 峰化放大器路径包括峰值放大器（210），阻抗变换网络（216）和相位延迟四分之一波长元件（226）。 该布置形成反向Doherty组合器，其中当加法节点（230）处的标称阻抗随着来自峰化放大器的传导增加而增加时，载波放大器的输出处的负载阻抗减小，以便将载波放大器保持在饱和点 随着输入信号（232）增加，并且导致相对于常规Doherty方法所需的相位延迟元件的数量的减少。 在优选实施例中，载波和峰值放大器由级联级组成，并且被布置在公共集成电路管芯（304）上。 阻抗变换网络和相位延迟元件如输入分配器网络（308）一样设置在公共基板（306）上。
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公开(公告)号：US5898912A
公开(公告)日：1999-04-27
申请号：US673857
申请日：1996-07-01
申请人： Joseph P. Heck , Robert E. Stengel
发明人： Joseph P. Heck , Robert E. Stengel
CPC分类号： H04L25/063 , H03D3/008 , H03G3/3052
摘要： A receiver (300) includes input (I.sub.in), output (V.sub.out), forward path with filter (104, and 108), and feedback path with error amplifier (112) coupled into the forward path. Coupled to the feedback path is an error signal storage device (408, 508). A control circuit (320) responsive to input signal amplitude couples to the storage device (408, 508) and retrieves stored error signal information for use by the feedback path. During calibration, a forward path stage is stimulated with a plurality of signals of known amplitude to generate outputs (V.sub.out). The outputs are compared to a reference to generate error signals. Error signal values are stored in memory as a function of input signal amplitude. A plurality of error signal values are stored. During operation, stage input signals are detected and compared with the plurality of signals of known amplitude. Upon detection of a match, the error signal value associated with the signal of interest is retrieved from memory and employed during DC offset compensation.
摘要翻译： 接收器（300）包括输入（Iin），输出（Vout），具有滤波器（104和108）的前向路径以及耦合到前向路径中的误差放大器（112）的反馈路径。 耦合到反馈路径的是误差信号存储装置（408,508）。 响应于输入信号幅度的控制电路（320）耦合到存储设备（408,508），并且检索所存储的误差信号以供反馈路径使用。 在校准期间，通过已知幅度的多个信号刺激正向路径级以产生输出（Vout）。 将输出与参考值进行比较以产生误差信号。 误差信号值作为输入信号幅度的函数存储在存储器中。 存储多个误差信号值。 在操作期间，检测舞台输入信号并与已知幅度的多个信号进行比较。 在检测到匹配时，从存储器检索与感兴趣的信号相关联的误差信号值，并在DC偏移补偿期间采用。
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公开(公告)号：US5379008A
公开(公告)日：1995-01-03
申请号：US25458
申请日：1993-03-03
CPC分类号： H03H7/06
摘要： An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The first (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits very low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.
摘要翻译： 电子电路（300）包括耦合在一起的第一（302）和第二（304）可变阻抗器件。 第一（302）和第二（304）可变阻抗装置被设计成使得每个展现出相对于另一个绕电子电路的工作点基本上相反的传递函数。 这提供了具有非常低失真特性的电子电路。 诸如可调谐滤波器，压控振荡器（VCO），接收器等的电路将受益于使用具有这种低失真特性的电子电路（300）。
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46.发明授权Receiver sensitivity threshold extended with the combination of an unmodulated signal with the received signal 失效接收机灵敏度阈值与未调制信号与接收信号的组合扩展
公开(公告)号：US5303411A
公开(公告)日：1994-04-12
申请号：US883820
申请日：1992-05-11
申请人： Robert E. Stengel , Paul D. Marko
发明人： Robert E. Stengel , Paul D. Marko
IPC分类号： H04B1/10
CPC分类号： H04B1/10
摘要： A receiver (10) is provided where an information signal (11) is received (12) and examined to determine (20) its signal strength. When the signal strength is at least equal to a threshold, an unmodulated signal (40) is added to the received signal to improve the sensitivity of the receiver.
摘要翻译： 提供接收机（10），其中接收信息信号（11）（12）并进行检查以确定（20）其信号强度。 当信号强度至少等于阈值时，将未调制信号（40）加到接收信号上以提高接收机的灵敏度。
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公开(公告)号：US5166857A
公开(公告)日：1992-11-24
申请号：US812927
申请日：1991-12-24
摘要： An integrated switch (100) includes a first input port (102), a second input port (112) and an output port (106). The integrated switch (100) comprises a first electronically-tunable integrated capacitor (104) having a control line (108) for selectively coupling the first input port (102) to the output port (106). The switch (100) also includes a second electronically-tunable integrated capacitor (110) having a control line (108) for selectively coupling the second input port (112) to the output port (106).
摘要翻译： 集成开关（100）包括第一输入端口（102），第二输入端口（112）和输出端口（106）。 集成开关（100）包括具有用于选择性地将第一输入端口（102）耦合到输出端口（106）的控制线（108）的第一电子可调谐集成电容器（104）。 开关（100）还包括具有用于选择性地将第二输入端口（112）耦合到输出端口（106）的控制线（108）的第二电子可调谐集成电容器（110）。
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公开(公告)号：US5151709A
公开(公告)日：1992-09-29
申请号：US419551
申请日：1989-10-10
申请人： Quirino Balzano , Robert E. Stengel
发明人： Quirino Balzano , Robert E. Stengel
摘要： An antenna (10) capable of receiving signals of various frequencies includes a series of superconducting antenna segments and decouplers disposed between each adjacent pair of antenna segments for selectively decoupling at least one antenna segment from the antenna (10) in response to the frequency of the signal received.
摘要翻译： 能够接收各种频率的信号的天线（10）包括一系列超导天线段和设置在每个相邻天线段对之间的去耦器，用于响应于所述天线（10）的频率选择性地将天线段与天线（10）分离 收到信号。
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公开(公告)号：US4785263A
公开(公告)日：1988-11-15
申请号：US55207
申请日：1987-05-28
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1243 , H03B2200/0008 , H03B2200/0032
摘要： A Ga As FET oscillator includes an FET having gate-drain and source connections. A tuned circuit is connected to the FET gate. Bias voltage is supplied to the FET. A parallel-connected resistor and capacitor is connected to the FET source. A Schottky diode is connected across the FET gate-source junction and the parallel connected resistor and capacitor, with its anode connected to the FET gate and its cathode connected to the resistor and capacitor. The Schottky diode limits the positive voltage across the gate-source junction of the Ga As FET to prevent gate-source current flow.
摘要翻译： GaAs FET振荡器包括具有栅极 - 漏极和源极连接的FET。 调谐电路连接到FET门。 偏置电压被提供给FET。 并联电阻和电容连接到FET源。 肖特基二极管连接在FET栅极 - 源极结和并联的电阻和电容之间，其阳极连接到FET栅极，其阴极连接到电阻和电容。 肖特基二极管限制Ga As FET栅极 - 源极结两端的正电压，以防止栅极 - 源极电流流动。
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50.发明申请METHOD AND APPARATUS FOR A MULTI-ANTENNA DEVICE THAT USES A SINGLE BASEBAND FILTER AND ANALOG-TO-DIGITAL CONVERTER 有权使用单个基带滤波器和模拟数字转换器的多天线设备的方法和装置公开(公告)号：US20130114588A1
公开(公告)日：2013-05-09
申请号：US13288212
申请日：2011-11-03
CPC分类号： H04B1/0064 , H04B7/0837
摘要： A multi-antenna device (200) comprising a set of antennas (210-214), a set of receivers (220-224), a multiplexer (270), a baseband filter (242), an analog-to-digital converter (244), and a de-multiplexer (272). The receivers (220-224) can be linked to the antennas (210-214) in a one-to-one manner. The multiplexer (270) can generate a composite analog signal from a set of different analog signals, one received from different ones of the antennas (210-214). The baseband filter (242) can filter the composite analog signal. The analog-to-digital converter (244) can convert the composite analog signal after being filtered by the baseband filter into a composite digital signal. The de-multiplexer (272) can generate a set of different digital signals from the composite digital signal. Each of the different digital signals can correspond to one of the different analog signals in a one-to-one manner.
摘要翻译： 一种多天线设备（200），包括一组天线（210-214），一组接收机（220-224），多路复用器（270），基带滤波器（242），模数转换器 244）和解复用器（272）。 接收器（220-224）可以以一对一的方式链接到天线（210-214）。 多路复用器（270）可以从一组不同的模拟信号中产生一个复合模拟信号，一组从不同的天线（210-214）接收。 基带滤波器（242）可以对复合模拟信号进行滤波。 模数转换器（244）可以将由基带滤波器滤波后的复合模拟信号转换为复合数字信号。 解复用器（272）可以从复合数字信号产生一组不同的数字信号。 每个不同的数字信号可以以一对一的方式对应于不同的模拟信号之一。
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