-
公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译： 一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。 每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。 首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。 数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。 在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。 这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。
-
42.发明授权Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code 有权用于提供两位符号总线纠错码的系统，方法和计算机程序产品公开(公告)号：US07721178B2
公开(公告)日：2010-05-18
申请号：US11421534
申请日：2006-06-01
申请人： Timothy J. Dell , Patrick J. Meaney
发明人： Timothy J. Dell , Patrick J. Meaney
IPC分类号： H03M13/29
CPC分类号： H03M13/033 , H03M13/13 , H03M13/19 , H03M13/618
摘要： Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.
摘要翻译： 用于提供嵌套式2位符号总线纠错码的系统，方法和计算机程序产品。 方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收汉明距离n码。 通过在符号列的基础上迭代地添加H矩阵位的行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离n码被保留为 符号校正码H矩阵。
-
43.发明申请公开(公告)号：US20090217110A1
公开(公告)日：2009-08-27
申请号：US12036697
申请日：2008-02-25
IPC分类号： G06F11/30
CPC分类号： G06F11/0721 , G06F11/076
摘要： A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.
摘要翻译： 一种用于处理处理器中的错误的系统，包括：错误计数器，通过计数器和可操作以确定第一错误是否有效的处理部分，响应于确定第一错误是活动的，增加错误计数器，增加通过计数器 响应于确定已经检查了所有错误，并且响应于确定通过计数器大于或等于通过计数阈值来清除错误计数器。
-
44.发明申请Collecting Failure Information On Error Correction Code (ECC) Protected Data 有权收集有关错误纠正码（ECC）受保护数据的故障信息公开(公告)号：US20090164874A1
公开(公告)日：2009-06-25
申请号：US12360402
申请日：2009-01-27
CPC分类号： G06F11/10
摘要： Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译： 纠错码（ECC）调试的方法和手段可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。
-
公开(公告)号：US20070300040A1
公开(公告)日：2007-12-27
申请号：US11425398
申请日：2006-06-21
CPC分类号： G06F13/37
摘要： Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.
摘要翻译： 公开了一种用于通过SMP计算机系统的共享资源在多个管线之间仲裁的方法和装置。 该计算机包括延迟仲裁的逻辑，直到稍后的管道，以帮助减少每个管道的延迟。 此外，引入了重试标签的概念，以便更好地优先避免锁定。 该系统还包括循环令牌来管理被拒绝的请求，以使冲突更加公平。 虽然采用的处理逻辑特别适用于交叉询问，但逻辑可以扩展到其他公共资源。 所示的SMP计算机系统还具有自校正逻辑，以保持良好的循环令牌。
-
46.发明授权Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface 失效用于源同步波流水线接口的接收机延迟检测和延迟最小化的方法公开(公告)号：US06954870B2
公开(公告)日：2005-10-11
申请号：US10096382
申请日：2002-03-12
申请人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005
摘要： A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.
摘要翻译： 提供校准弹性界面的方法以通过界面自动实现最小的循环延迟。 现有的自对准接口（即弹性接口）用于在一个周期内去偏移，并且在给定的编程的目标周期上对数据进行分段以使其达到。 但是，这个目标周期必须提前计算，并且可能会大于需要的时间，从而在接口上造成更多的延迟。 该方法用于确定最早的目标周期（带或不带附加保护带）。 该目标周期用于自动调整接口以实现最早的目标周期。 最早的目标周期的确定可以进行一次，连续或使用样本窗口。 该方法还可用于在其边界具有频率乘法器或相移的接口。
-
公开(公告)号：US06457154B1
公开(公告)日：2002-09-24
申请号：US09451261
申请日：1999-11-30
IPC分类号： G11C2900
CPC分类号： G06F11/1016
摘要： Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.
摘要翻译： 根据纠错码在数据字的发送期间检测不正确的错误。 然后，从检测到的不可校正错误中识别任何地址故障。 此外，从检测到的不可校正错误中检测到地址故障以及不可校正的存储器数据故障。 此外，地址奇偶校验位不需要存储到存储器中。
-
公开(公告)号：US5631915A
公开(公告)日：1997-05-20
申请号：US468277
申请日：1995-06-06
申请人： Patrick J. Meaney , Chin-Long Chen
发明人： Patrick J. Meaney , Chin-Long Chen
CPC分类号： G06F11/1012 , H03M13/13
摘要： Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit positions. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
摘要翻译： 错误检测和校正电路，经过优化，可减少校正单个错误所需的时间并检测是否存在不可校正的错误，使用优化的H-Matrix并提供减少的逻辑电路。 可纠正的误差综合征被定义为包括奇数个，并且当检测到偶数个错误时，不可校正错误检测电路产生不可校正错误指示。 可校正错误综合征被定义为在一组相应位位置中的每一个中具有预定义的1和0的组合，以及在其它位位置中具有不同的1和0的组合。 仅包括零的错误综合征被指定为无错误状态的指示。 提供逻辑电路，其实现具有减少的逻辑门集合的错误检测和校正电路。
-
公开(公告)号：US5455931A
公开(公告)日：1995-10-03
申请号：US155178
申请日：1993-11-19
CPC分类号： G06F17/5031 , G06F1/10
摘要： A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
摘要翻译： 一种具有增强的定时故障诊断和非层次功能的数据处理系统的时钟调整系统和方法。 通用和单独的相位调整功能均可确保分布在计算机系统中的时钟脉冲的可编程调谐，从而便于通过在逻辑路径之间移动时序余量来将定时裕度故障隔离到特定的时钟信号或增强系统性能。 讨论了单时钟和双时钟数据处理以及每个时钟调整实施例。
-
公开(公告)号：US08898511B2
公开(公告)日：2014-11-25
申请号：US12822964
申请日：2010-06-24
申请人： Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens , Lisa C. Gower
发明人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。
-
-
-
-
-
-
-
-
-
搜索结果
87 条记录 (耗时 0.029 秒)
