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1.发明授权Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface 失效用于源同步波流水线接口的接收机延迟检测和延迟最小化的方法公开(公告)号：US06954870B2
公开(公告)日：2005-10-11
申请号：US10096382
申请日：2002-03-12
申请人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005
摘要： A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.
摘要翻译： 提供校准弹性界面的方法以通过界面自动实现最小的循环延迟。 现有的自对准接口（即弹性接口）用于在一个周期内去偏移，并且在给定的编程的目标周期上对数据进行分段以使其达到。 但是，这个目标周期必须提前计算，并且可能会大于需要的时间，从而在接口上造成更多的延迟。 该方法用于确定最早的目标周期（带或不带附加保护带）。 该目标周期用于自动调整接口以实现最早的目标周期。 最早的目标周期的确定可以进行一次，连续或使用样本窗口。 该方法还可用于在其边界具有频率乘法器或相移的接口。
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公开(公告)号：US06934867B2
公开(公告)日：2005-08-23
申请号：US10150231
申请日：2002-05-17
摘要： A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle. The target cycle is fed back into the design and the data is received synchronously, also provided is a test to ensure that the data arrives synchronously.
摘要翻译： 提供校准接口的方法，以便在多个自对准接口之间保持同步数据到达时自动实现最小的周期延迟。 独立的自对准接口可以对数据位进行偏移，并使它们到达最小周期边界。 但是，如果所有接口都没有在同一周期内到达，则SMP设计可能无法正常工作。 例如，在AMP节点上使用单个控制芯片和多个数据芯片，控制芯片通常会向数据流芯片发出控制。 如果到达弹性接口的数据与控件不同步，则数据路由不正确。 该方法采用校准模式来确定在弹性接口上接收数据的最新周期，并计算所有接口的目标周期以匹配该最新周期。 目标周期被反馈到设计中并且同步地接收数据，还提供了确保数据同步到达的测试。
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公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译： 嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力 设备。 作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。 每次存储器寻址时，测试模式都会旋转。 测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。 存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。 可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。
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公开(公告)号：US06748565B1
公开(公告)日：2004-06-08
申请号：US09676828
申请日：2000-10-02
IPC分类号： G01R3128
CPC分类号： H04L7/0008 , G01R31/31725 , H04L7/0037
摘要： An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.
摘要翻译： 本发明的一个示例性实施例是一种用于在数据处理系统中配置系统周期时间的方法和装置，其中至少一个主锁存时钟产生主锁存时钟信号，以及至少一个从锁存时钟产生从锁存时钟信号。 在系统硬件测试期间检测到定时错误。 基于主锁存时钟信号和从锁存时钟信号中的至少一个的误差来计算对系统定时的调整。 基于计算来调整主锁存时钟信号和从锁存时钟信号中的至少一个的接通周期边缘，同时保持主锁存时钟信号和从锁存时钟信号中的至少一个的对应的中间周期边沿 。
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5.发明授权Method of automating creation of a clock control distribution network in an integrated circuit floorplan 有权在集成电路平面图中自动创建时钟控制分配网络的方法公开(公告)号：US07979838B2
公开(公告)日：2011-07-12
申请号：US12032517
申请日：2008-02-15
申请人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
发明人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
摘要翻译： 在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。 在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地利用 分段锁存器，消除不必要的电源和区域使用。 通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。
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公开(公告)号：US4553049A
公开(公告)日：1985-11-12
申请号：US540072
申请日：1983-10-07
IPC分类号： G01R31/26 , G01R31/28 , G01R31/319 , H01L21/66 , H01L21/822 , H01L27/04 , H03K19/092 , H03K17/62
CPC分类号： G01R31/31924 , G01R31/31905
摘要： Integrated circuit logic chips often oscillate during testing because the large unbypassed inductance of the test fixture causes off-chip driver switching noise to be fed back to the logic chip power supply. Oscillation may be prevented by adding an inhibit receiver and an off-chip driver inhibit network to the logic chip. The off-chip driver inhibit network provides a fan out path from the inhibit receiver to each off-chip driver. In response to an inhibit signal applied to the inhibit receiver, the inhibit network forces each of the off-chip drivers to the same logical state, the logic state being the natural logic state assumed by the off-chip drivers upon initial application of power to the chip. The driver inhibit receiver and inhibit network are employed to prevent oscillation at chip power-on, during driver and receiver parametric testing and during input test pattern tests.
摘要翻译： 集成电路逻辑芯片在测试期间经常振荡，因为测试夹具的大的非旁路电感导致芯片外驱动器开关噪声反馈到逻辑芯片电源。 可以通过向禁止接收器和片外驱动器禁止网络到逻辑芯片来防止振荡。 片外驱动器禁止网络提供从禁止接收器到每个片外驱动器的扇出路径。 响应于施加到禁止接收器的抑制信号，禁止网络迫使每个片外驱动器处于相同的逻辑状态，逻辑状态是由片外驱动器在初次施加电源时假定的自然逻辑状态 芯片。 在驱动器和接收机参数测试期间以及在输入测试模式测试期间，驱动器禁止接收器和禁止网络用于防止芯片上电时的振荡。
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