公开(公告)号：US20070283223A1

公开(公告)日：2007-12-06

申请号：US11421538

申请日：2006-06-01

申请人： Timothy J. Dell ,  Patrick J. Meaney

发明人： Timothy J. Dell ,  Patrick J. Meaney

IPC分类号： G11C29/00

CPC分类号： G06F11/10 ,  H03M13/19 ,  H03M13/356 ,  H03M13/618 ,  H03M13/6306 ,  H03M13/6368 ,  H04L1/0063 ,  H04L2001/0095

摘要： Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the original checkbits and the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

摘要翻译： 用于提供嵌套两比特符号总线纠错码方案的系统，方法和计算机程序产品，用于在两个或多个传输中通过总线进行传输。 方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收包括原始检验位的汉明距离n码。 定义符号校正码H矩阵框架，包括指定原始校验位的位位置和与符号校正码相关联的附加校验位。 指定位位置，使得原始校验位和附加校验位处于在第一次传送之后的传送中通过总线传送的比特位置。 使用由框架指示的比特位置，通过在符号列上迭代地添加H矩阵比特行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离 n代码被保留为符号校正码H矩阵的子集。

公开(公告)号：US20070283208A1

公开(公告)日：2007-12-06

申请号：US11421537

申请日：2006-06-01

申请人： Timothy J. Dell ,  Patrick J. Meaney

发明人： Timothy J. Dell ,  Patrick J. Meaney

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  H03M13/098 ,  H03M13/19

摘要： Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code for transfer over a bus in two or more transfers Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

摘要翻译： 用于提供用于在两个或多个传输中通过总线传送的嵌套两比特符号总线纠错码的系统，方法和计算机程序产品方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收包括原始检验位的汉明距离n码。 定义符号校正码H矩阵框架，包括指定原始校验位的位位置和与符号校正码相关联的附加校验位。 指定位位置，使得附加检验位处于在第一次传送之后的传输中通过总线传送的位位置。 使用由框架指示的比特位置，通过在符号列上迭代地添加H矩阵比特行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离 n代码被保留为符号校正码H矩阵的子集。

公开(公告)号：US20070283207A1

公开(公告)日：2007-12-06

申请号：US11421532

申请日：2006-06-01

申请人： Timothy J. Dell ,  Patrick J. Meaney

发明人： Timothy J. Dell ,  Patrick J. Meaney

IPC分类号： H03M13/00

CPC分类号： H03M13/098 ,  H03M13/19 ,  H03M13/2906

摘要： Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

摘要翻译： 用于提供嵌套两比特符号总线纠错码方案的系统，方法和计算机程序产品，用于在两个或多个传输中通过总线进行传输。 方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收包括原始检验位的汉明距离n码。 定义符号校正码H矩阵框架，包括指定原始校验位的位位置和与符号校正码相关联的附加校验位。 指定位位置，使得附加检验位处于在第一次传送之后的传输中通过总线传送的位位置。 使用由框架指示的比特位置，通过在符号列上迭代地添加H矩阵比特行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离 n代码被保留为符号校正码H矩阵的子集。

公开(公告)号：US07721178B2

公开(公告)日：2010-05-18

申请号：US11421534

申请日：2006-06-01

申请人： Timothy J. Dell ,  Patrick J. Meaney

发明人： Timothy J. Dell ,  Patrick J. Meaney

IPC分类号： H03M13/29

CPC分类号： H03M13/033 ,  H03M13/13 ,  H03M13/19 ,  H03M13/618

摘要： Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

摘要翻译： 用于提供嵌套式2位符号总线纠错码的系统，方法和计算机程序产品。 方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收汉明距离n码。 通过在符号列的基础上迭代地添加H矩阵位的行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离n码被保留为 符号校正码H矩阵。

公开(公告)号：US20070283229A1

公开(公告)日：2007-12-06

申请号：US11421534

申请日：2006-06-01

申请人： Timothy J. Dell ,  Patrick J. Meaney

发明人： Timothy J. Dell ,  Patrick J. Meaney

IPC分类号： H03M13/00

CPC分类号： H03M13/033 ,  H03M13/13 ,  H03M13/19 ,  H03M13/618

摘要： Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

摘要翻译： 用于提供嵌套式2位符号总线纠错码的系统，方法和计算机程序产品。 方法包括构建嵌套纠错码（ECC）方案。 该方法包括接收汉明距离n码。 通过在符号列的基础上迭代地添加H矩阵位的行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离n码被保留为 符号校正码H矩阵。

公开(公告)号：US20130339808A1

公开(公告)日：2013-12-19

申请号：US13523633

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

IPC分类号： G06F11/20

CPC分类号： G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.

摘要翻译： 实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。 实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误 记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置 第二个位线地址。

公开(公告)号：US20130191703A1

公开(公告)日：2013-07-25

申请号：US13353879

申请日：2012-01-19

申请人： Patrick J. Meaney ,  William J. Clarke ,  Eldee Stephens ,  Judy S. Johnson

发明人： Patrick J. Meaney ,  William J. Clarke ,  Eldee Stephens ,  Judy S. Johnson

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1004 ,  G06F11/1076 ,  G06F2211/109

摘要： Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.

摘要翻译： 提供了包括多个存储器件的独立存储器（RAIM）系统的冗余阵列中的动态分级存储器件保护。 确定多个存储器件中的第一故障存储器件的第一严重性级别。 第一故障存储设备与用于将第一故障存储设备的位置传送到纠错码（ECC）的标识符相关联。 确定多个存储器件中的第二故障存储器件的第二严重性级别。 确定第二严重性级别高于第一严重性级别。 基于确定第二严重性级别高于第一严重性级别，去除来自第一故障存储器设备的标识符。 基于确定第二严重性级别高于第一严重性级别，将标识符应用于第二故障存储设备。

公开(公告)号：US08271932B2

公开(公告)日：2012-09-18

申请号：US12823010

申请日：2010-06-24

申请人： Dean G. Bair ,  Patrick J. Meaney ,  Luis A. Lastras-Montano ,  Alia D. Shah ,  Eldee Stephens

发明人： Dean G. Bair ,  Patrick J. Meaney ,  Luis A. Lastras-Montano ,  Alia D. Shah ,  Eldee Stephens

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G06F11/1008 ,  G06F11/108

摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.

摘要翻译： 一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记 通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。

公开(公告)号：US20110320914A1

公开(公告)日：2011-12-29

申请号：US12822503

申请日：2010-06-24

申请人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

发明人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

IPC分类号： G06F11/10

CPC分类号： G06F11/1004 ,  G06F11/108

摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。

公开(公告)号：US20110320869A1

公开(公告)日：2011-12-29

申请号：US12822964

申请日：2010-06-24

申请人： Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

发明人： Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

IPC分类号： G06F11/07 ,  G06F11/14

CPC分类号： G06F11/1666 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.

摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。