公开(公告)号：US07554523B2

公开(公告)日：2009-06-30

申请号：US11188809

申请日：2005-07-25

Applicant: Paul Chang ,  Yu-Chi Lin

Inventor： Paul Chang ,  Yu-Chi Lin

IPC: G09G5/00

CPC classification number: G06F1/1616 ,  G06F1/1686

Abstract: The present invention relates to a peripheral device for image display, which comprises a hollow spot for holding the peripheral device, which then comprises a base and a shaft, wherein the shaft was located on the base, of which the shaft and the slot are a hole and shaft assembly case and the shaft maintains its degree of freedom in the slot, wherein the base can not only rotate but also slide. In addition, the base comprises at least one positioning hole and the image display device comprises at least one positioning pin, when the positioning hole is fitted by the positioning pin, the degree of freedom of the rotation is thus restricted. In comparison with prior art, the ease of use is obvious, and the design flexibility is abundant.

Abstract translation: 本发明涉及一种用于图像显示的外围设备，其包括用于保持外围设备的中空点，该中空点包括基座和轴，其中轴位于基座上，其中轴和槽是 孔和轴组件壳体，并且轴保持其在槽中的自由度，其中基座不仅可旋转而且滑动。 此外，基座包括至少一个定位孔，并且图像显示装置包括至少一个定位销，当定位孔由定位销配合时，因此限制了旋转的自由度。 与现有技术相比，易用性明显，设计灵活性丰富。

公开(公告)号：US20080136503A1

公开(公告)日：2008-06-12

申请号：US11618900

申请日：2006-12-31

Applicant: Stephen Chi-Wang Au ,  Arya Behzad ,  Paul Chang

Inventor： Stephen Chi-Wang Au ,  Arya Behzad ,  Paul Chang

IPC: G05F3/02

CPC classification number: H03F3/45475 ,  H03F2203/45048

Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.

Abstract translation: 公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。 一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。 可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。 过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。 可以基于产生的输出电流来确定可变电阻器两端产生的电压。

公开(公告)号：US20070246794A1

公开(公告)日：2007-10-25

申请号：US11821234

申请日：2007-06-22

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Hsueh ,  Vladimir Rodov

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07250668B2

公开(公告)日：2007-07-31

申请号：US11040180

申请日：2005-01-20

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L29/00

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

公开(公告)号：US20060157815A1

公开(公告)日：2006-07-20

申请号：US11040180

申请日：2005-01-20

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Hsueh ,  Vladimir Rodov

IPC: H01L29/00

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US20050232159A1

公开(公告)日：2005-10-20

申请号：US11133073

申请日：2005-05-18

Applicant: Jeong Joo ,  Fred King ,  Patrick Riley ,  Aart Konynenberg ,  Paul Chang

Inventor： Jeong Joo ,  Fred King ,  Patrick Riley ,  Aart Konynenberg ,  Paul Chang

IPC: G06F1/26 ,  H04L1/00

CPC classification number: G06F1/189 ,  G06F1/181 ,  H04L43/50

Abstract: A network test architecture includes a plurality of modules for performing a plurality of functions, each of the plurality of modules having a unique identifier. An additional module for performing an additional function has an additional unique identifier. A control bus is connected among the plurality of modules; a data bus is connected among the plurality of modules; and a power bus is connected among the plurality of modules. A controller controls operation, data transmission, and powering of the plurality of modules and the additional module, respectively, through the control bus, the data bus, and the power bus, the controller using the unique identifier and the additional unique identifier of the plurality of modules upon simultaneous connection of the control bus, the data bus, and the power bus to the additional module.

公开(公告)号：US06624030B2

公开(公告)日：2003-09-23

申请号：US09742262

申请日：2000-12-19

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov ,  Charles Lin

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov ,  Charles Lin

IPC: H01L21336

CPC classification number: H01L29/861 ,  H01L21/2815 ,  H01L29/0696 ,  H01L29/6609 ,  H01L29/7802

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract translation: 一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域 主要表面毗邻门。 第二导电类型的多个通道每个都邻接源极/漏极区并在栅极下方延伸，每个沟道横向渐变，其中沟道区域与第一导电类型的衬底分离出倾斜的P-N结。 在制造垂直半导体整流器件时，在半导体表面上形成一个部分离子掩模，该掩模具有倾斜表面，该倾斜表面改变通过该掩模的离子的路径长度以形成横向渐变的沟道区。

公开(公告)号：US06579144B1

公开(公告)日：2003-06-17

申请号：US10189002

申请日：2002-07-05

Applicant: Paul Chang

Inventor： Paul Chang

IPC: A63H300

CPC classification number: A63H9/00

Abstract: A method of manufacturing an environmental protective paper doll includes the steps of using recycle paper as the manufacturing material; adding appropriate proportion of water to the paper pulp after a slight filtering to make a paste; pressing the vacuum mold on the protruded mold plate after tying the net; submerging in a trough containing the pasty paper pulp; drawing out the liquid in the vacuum shaping mold to facilitate the formation of an embryo layer with appropriate thickness on the tying net of the protrusion member; engaging the upper mold and the lower mold together and preliminarily removing the water content; baking the semi-finished embryo layer for dehydration; pasting the front and rear halves with glue; trimming the rough edge and coating the paper surface with a layer of golden paint to increase the hardness of the surface; and then painting with the stylish colors and forming the paper doll.

Abstract translation: 制造环保纸娃娃的方法包括以回收纸作为制造材料的步骤; 在轻轻过滤后加入适量的水分至纸浆中制成糊状物; 扣网后将真空模压在突出模板上; 浸没在含有糊状纸浆的槽中; 抽出真空成型模具中的液体，以便在突出部件的网状网上形成适当厚度的胚层; 将上模和下模结合在一起并预先除去含水量; 烘干半成品胚层脱水; 用胶水粘贴前后两半; 修剪粗糙的边缘，并用一层金色涂料涂覆纸张表面以增加表面的硬度; 然后用时尚的颜色绘画并形成纸娃娃。

公开(公告)号：US06515330B1

公开(公告)日：2003-02-04

申请号：US10037495

申请日：2002-01-02

Applicant: Gary M. Hurtz ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Paul Chang ,  Ching-Lang Chiang

Inventor： Gary M. Hurtz ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Paul Chang ,  Ching-Lang Chiang

IPC: H01L2976

CPC classification number: H01L29/7811 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/861

Abstract: A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.

Abstract translation: 半导体限流器件由两端垂直N（P）沟道MOSFET器件提供，其栅极，体和源极端子连接在一起作为阳极，漏极端子作为阴极。 使用离子注入来定制主体的掺杂特性，耗尽区夹紧以限制电流。 主体包括浅植入物以形成MOS通道，并通过隔离屏蔽通道区域的间隔物进行额外的深度注入。 注入较高的能量并且以锐角，深的注入突出到垂直MOSFET的常规电流通路中。

公开(公告)号：US06448160B1

公开(公告)日：2002-09-10

申请号：US09544730

申请日：2000-04-06

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L2144

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor. The channel regions are defined by using the photoresist mask for the gate oxide with the photoresist mask isotropically etched to expose a peripheral portion of the gate oxide (and gate electrode) with ions thereafter implanted through the exposed gate for forming the channel region. The source/drain (e.g. source) regions can be formed by ion implantation or by out-diffusion from a doped polysilicon layer.

Abstract translation: 一种半导体整流装置，其模拟低正向压降肖特基二极管的特性，并能够具有小于1A至大于1000A电流的多种电气特性，具有可调击穿电压。 制造过程提供了操作参数的均匀性和可控性，高产量和容易变化的装置尺寸。 该器件包括在一个表面上具有保护环的半导体本体，以限定其中可选地形成多个导电插塞的器件区域。 在保护环和导电插塞之间是形成MOS晶体管的多个源极/漏极，栅极和沟道元件，其与下面的衬底起作用。 通过使用用于栅极氧化物的光致抗蚀剂掩模来限定沟道区，其中光致抗蚀剂掩模被各向同性蚀刻以暴露栅极氧化物（和栅电极）的外围部分，然后通过暴露的栅极注入用于形成沟道区的离子。 源极/漏极（例如源极）区域可以通过离子注入或通过从掺杂多晶硅层向外扩散来形成。