公开(公告)号：US06743703B2

公开(公告)日：2004-06-01

申请号：US10238104

申请日：2002-09-09

Applicant: Vladimir Rodov ,  Paul Chang ,  Jianren Bao ,  Wayne Y. W. Hsueh ,  Arthur Ching-Lang Chiang ,  Geeng-Chuan Chern

Inventor： Vladimir Rodov ,  Paul Chang ,  Jianren Bao ,  Wayne Y. W. Hsueh ,  Arthur Ching-Lang Chiang ,  Geeng-Chuan Chern

IPC: H01L2974

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract translation: 双端功率二极管具有改进的反向偏压击穿电压，并且导通电阻包括具有两个相对表面的半导体本体和它们之间的超结结构，所述超结结构包括多个交替的P和N掺杂区域，其大致垂直于两个表面排列。 P和N掺杂区域可以是平行条纹或网状物，每个区域被相反导电类型的掺杂材料包围。 与一个表面相关联的二极管结可以是具有将阳极区域连接到超结构结构的栅极控制沟道区域的阳极区域。 或者，二极管结可以包括与该表面形成肖特基结的金属。 超结构在阴极内并与阳极间隔开。 间隔可以在器件制造过程中变化。

公开(公告)号：US06537860B2

公开(公告)日：2003-03-25

申请号：US09739732

申请日：2000-12-18

Applicant: Hidenori Akiyama ,  Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Haru Ohkawa ,  Yasuo Ohtsuki ,  Vladimir Rodov

Inventor： Hidenori Akiyama ,  Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Haru Ohkawa ,  Yasuo Ohtsuki ,  Vladimir Rodov

IPC: H01L21332

CPC classification number: H01L29/6609 ,  H01L29/0619 ,  H01L29/7391 ,  H01L29/861

Abstract: A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

公开(公告)号：USRE35094E

公开(公告)日：1995-11-21

申请号：US974262

申请日：1992-11-10

Applicant: Tsung-Ching Wu ,  Geeng-Chuan Chern

Inventor： Tsung-Ching Wu ,  Geeng-Chuan Chern

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window. The window is filled with a thin oxide layer and the floating gate is formed so that its edge lies over a portion of the window. Control gates, sources and drains are formed last.

公开(公告)号：US20110223729A1

公开(公告)日：2011-09-15

申请号：US13108630

申请日：2011-05-16

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

IPC: H01L21/8234

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07964933B2

公开(公告)日：2011-06-21

申请号：US11821234

申请日：2007-06-22

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L21/76

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07084453B2

公开(公告)日：2006-08-01

申请号：US10850300

申请日：2004-05-19

Applicant: Geeng-Chuan Chern ,  Amitay Levi ,  Dana Lee

Inventor： Geeng-Chuan Chern ,  Amitay Levi ,  Dana Lee

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11539 ,  Y10S438/981

Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.

公开(公告)号：US06967372B2

公开(公告)日：2005-11-22

申请号：US09916618

申请日：2001-07-26

Applicant: Geeng-Chuan Chern

Inventor： Geeng-Chuan Chern

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. Control gates are each formed with a substantially vertical face portion by covering a portion of a conductive layer with a protective layer, and performing an anisotropic etch to remove the exposed portion of the conductive layer. An insulation sidewall spacer is formed against the vertical face portion. The control gates have protruding portions that extend over the floating gates.

Abstract translation: 一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，该半导体衬底在衬底上具有多个间隔开的隔离区域和在衬底上彼此基本上平行的有源区域。 浮动栅极形成在每个有源区域中。 每个控制栅极通过用保护层覆盖导电层的一部分并且执行各向异性蚀刻以去除导电层的暴露部分，形成有基本垂直的面部。 绝缘侧壁隔离件形成为抵靠垂直面部分。 控制门具有在浮动栅极上延伸的突出部分。

公开(公告)号：US06765264B1

公开(公告)日：2004-07-20

申请号：US10446246

申请日：2003-05-27

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov ,  Charles Lin

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov ,  Charles Lin

IPC: H01L2976

CPC classification number: H01L29/861 ,  H01L21/2815 ,  H01L29/0696 ,  H01L29/6609 ,  H01L29/7802

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract translation: 一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域 主要表面毗邻门。 第二导电类型的多个通道每个都邻接源极/漏极区并且在栅极下方延伸，每个沟道横向渐变，其中倾斜的PN结从第一导电类型的衬底分离沟道区。在制造垂直半导体整流器 在半导体的表面上形成部分离子掩模，其掩模具有倾斜表面，该倾斜表面改变通过掩模的离子的路径长度，以形成横向渐变的通道区域。

公开(公告)号：US06399996B1

公开(公告)日：2002-06-04

申请号：US09620074

申请日：2000-07-20

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L77095

CPC classification number: H01L29/66143 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/781 ,  H01L29/872

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, and a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body.

Abstract translation: 肖特基二极管包括一种导电类型的半导体本体，具有沟槽表面的半导体本体，以及在凹槽表面上形成与半导体本体的肖特基结的金属层。 半导体本体优选地包括具有沟槽表面的硅衬底，该硅衬底在由与半导体本体的导电类型相反的导电类型的保护环限定的器件区域上。

公开(公告)号：US06420225B1

公开(公告)日：2002-07-16

申请号：US09805815

申请日：2001-03-13

Applicant: Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

Inventor： Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

IPC: H01L218234

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract translation: 一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域 主要表面毗邻门。 第二导电类型的多个通道各自邻接源/漏区并在栅极下方延伸。