公开(公告)号：US20070201296A1

公开(公告)日：2007-08-30

申请号：US11679732

申请日：2007-02-27

申请人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

发明人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

IPC分类号： G11C8/00

CPC分类号： G06F12/0607

摘要： A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。 存储器装置包括至少两个存储体。 每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。 至少两个数据分组处理设备被分配给不同的存储体存取设备。

公开(公告)号：US20070006057A1

公开(公告)日：2007-01-04

申请号：US11171585

申请日：2005-06-30

申请人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

IPC分类号： G11C29/00

CPC分类号： G11C7/1006

摘要： Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.

摘要翻译： 提供了一种半导体存储器芯片，其包括存储器核心和具有解码，选择和调度电路装置的接口电路，用于从信号帧解码相应类型的数据信号，命令信号和地址信号，选择所需的动作 存储器芯片，分别对接收电路的存储器核心部分和解码信号进行调度。 接口电路还包括CRC位解码和校验单元以及保护电路，该保护电路用于保护存储器核心并根据由该接口电路产生的正确/不正确的信号来允许/禁止从接口电路到存储器核心的信号传输切换 CRC比特解码和校验单元根据通过根据定义的传输协议与插入到信号帧中的各个信息相关联的CRC比特来检查帧内的信息的结果。

公开(公告)号：US20060123265A1

公开(公告)日：2006-06-08

申请号：US11002148

申请日：2004-12-03

申请人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G06F1/04

CPC分类号： G11C5/04 ,  G11C5/063

摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

公开(公告)号：US20060095826A1

公开(公告)日：2006-05-04

申请号：US11261911

申请日：2005-10-31

申请人： Hermann Ruckerbauer ,  Doninique Savignac ,  Peter Gregorius ,  Christian Sichert ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Doninique Savignac ,  Peter Gregorius ,  Christian Sichert ,  Paul Wallner

IPC分类号： H04L1/18 ,  G08C25/02

CPC分类号： G11C5/063 ,  G06F11/1044 ,  G11C7/10 ,  G11C11/4093

摘要： A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

摘要翻译： 半导体存储器模块包括多个半导体存储器芯片。 每个半导体存储器芯片包括接口电路，其被配置为检测写入数据中的传输错误，并且还被配置为经由单独的信号路径输出用于重复发送被检测为错误的写入数据的重复请求信号。 该重复请求信号可以作为单位信号或作为多位信号（例如，串行地作为单独的信号线发送到上级存储器控制器）来发送。

公开(公告)号：US20060067157A1

公开(公告)日：2006-03-30

申请号：US10955177

申请日：2004-09-30

申请人： Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G11C8/00 ,  G11C5/06

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

摘要翻译： 本发明涉及一种具有两条时钟线的存储器件的存储器系统。 本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控​​制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线 向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回 到存储器控制器的读时钟输入。 存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

公开(公告)号：US07536528B2

公开(公告)日：2009-05-19

申请号：US11679609

申请日：2007-02-27

申请人： Paul Wallner ,  Chaitanya Dudha

发明人： Paul Wallner ,  Chaitanya Dudha

IPC分类号： G06F13/00

CPC分类号： G06F12/0607

摘要： A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.

摘要翻译： 存储器布置包括被配置为按照预定义的协议以数据分组的形式传输，编码和/或解码数据的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。

公开(公告)号：US20080068913A1

公开(公告)日：2008-03-20

申请号：US11856621

申请日：2007-09-17

申请人： Christian Sichert ,  Paul Wallner

发明人： Christian Sichert ,  Paul Wallner

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.

摘要翻译： 刷新存储器装置的存储单元的内容的方法包括经由存储器装置的接口或存储器装置的内部控制装置选择性地控制存储器装置的刷新装置，以刷新存储器装置的内容。

公开(公告)号：US20080028148A1

公开(公告)日：2008-01-31

申请号：US11496261

申请日：2006-07-31

申请人： Paul Wallner ,  Chaitanya Dudha

发明人： Paul Wallner ,  Chaitanya Dudha

IPC分类号： G06F12/00

CPC分类号： G06F12/023

摘要： An integrated memory device includes a memory core having a plurality of memory cells and a group of terminals for communication between the memory device and an external electronic device. A data buffer temporarily stores data. The data buffer is coupled to the group of terminals and to the memory core. The data buffer includes a plurality of data buffer sections. Each data buffer section is capable of temporarily storing at least one data frame and being accessible by a respective data buffer address. A data buffer control unit is also provided.

摘要翻译： 集成存储器件包括具有多个存储器单元的存储器芯和用于存储器件和外部电子器件之间的通信的一组端子。 数据缓冲器临时存储数据。 数据缓冲器耦合到终端组和存储器核心。 数据缓冲器包括多个数据缓冲器部分。 每个数据缓冲器部分能够临时存储至少一个数据帧并且可由相应的数据缓冲器地址访问。 还提供了数据缓冲器控制单元。

公开(公告)号：US20070204116A1

公开(公告)日：2007-08-30

申请号：US11679609

申请日：2007-02-27

申请人： Paul Wallner ,  Chaitanya Dudha

发明人： Paul Wallner ,  Chaitanya Dudha

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0607

摘要： A memory arrangement includes an interface configured to transmit coding and/or decoding data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing, the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.

摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式传输数据的编码和/或解码的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据的至少两个存储体存取器存取器件。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。

公开(公告)号：US20070076004A1

公开(公告)日：2007-04-05

申请号：US11242149

申请日：2005-10-04

申请人： Paul Wallner ,  Yukio Fukuzo ,  Christian Sichert ,  Paul Schmolz

发明人： Paul Wallner ,  Yukio Fukuzo ,  Christian Sichert ,  Paul Schmolz

IPC分类号： G06T1/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

摘要翻译： 信号作为串行信号帧传送的半导体存储器芯片包括提供存储器核心和接收接口之间的接口的帧解码器。 帧解码器包括用于根据解码的命令类型对包括在帧中的命令的类型进行解码的命令类型解码器，用于调度和准备用于核心的单个命令的存储器命令评估器/生成器，中间数据缓冲器命令评估器/生成器 用于调度和准备中间数据缓冲器的控制信号，以及用于准备和调度系统命令的系统命令评估器/发生器。 这些系统命令提供定时参数，以确保一帧内或帧之间的连续命令之间的时间间隔，并存储在系统模式寄存器中。 帧解码器的操作由帧时钟或同步解码器时钟信号进行边沿同步，该时钟信号与该帧时钟信号相对齐。