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162 条记录 (耗时 0.028 秒)

    Stepped-source LDMOS architecture
    43.
    发明授权
    Stepped-source LDMOS architecture 有权
    步进源LDMOS架构

    公开(公告)号：US08362557B2

    公开(公告)日：2013-01-29

    申请号：US12629362

    申请日：2009-12-02

    申请人： Jun Cai

    发明人： Jun Cai

    IPC分类号： H01L29/66

    CPC分类号： H01L29/0878 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

    摘要： A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

    摘要翻译： 半导体器件可以包括在半导体区域的工作顶表面附近的源极区域。 该装置还可以包括位于工作顶表面上方并位于源极和漏极区域之间的栅极的栅极。 源极区域和栅极可以至少部分地侧向地与工作顶部表面附近的主体区域重叠。 源极区域可以包括具有第一导电类型的第一部分，具有第二导电类型的第二部分和具有第二导电类型的第三部分。 第二部分可以横向位于第一和第三部分之间，并且可以穿透半导体区域到比第三部分更大的深度，但不超过第一部分。 至少部分地使用门的横向位置来确定第三部分的横向位置。

    Hybrid-mode LDMOS
    45.
    发明授权
    Hybrid-mode LDMOS 有权
    混合模式LDMOS

    公开(公告)号：US08329542B2

    公开(公告)日：2012-12-11

    申请号：US13278616

    申请日：2011-10-21

    申请人： Jun Cai

    发明人： Jun Cai

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7831 ,  H01L27/0705 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7817

    摘要： An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

    摘要翻译： MOS双极混合模式LDMOS器件具有主栅极输入和控制栅极输入，其中当两个栅极输入被使能时，器件工作在MOS模式，并且当主栅极输入被使能并且控制 门禁输入禁用。 器件可以驱动功率MOSFET的栅极，以在双极模式下提供功率MOSFET所需的高电流，并且在MOS模式下提供功率MOSFET栅极之间的电源电压和接地之间的全面切换。

    HYBRID-MODE LDMOS
    46.
    发明申请
    HYBRID-MODE LDMOS 有权
    混合模式LDMOS

    公开(公告)号：US20120094458A1

    公开(公告)日：2012-04-19

    申请号：US13278616

    申请日：2011-10-21

    申请人： Jun Cai

    发明人： Jun Cai

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7831 ,  H01L27/0705 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7817

    摘要： An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

    摘要翻译： MOS双极混合模式LDMOS器件具有主栅极输入和控制栅极输入，其中当两个栅极输入被使能时，器件工作在MOS模式，并且当主栅极输入被使能并且控制 门禁输入禁用。 器件可以驱动功率MOSFET的栅极，以在双极模式下提供功率MOSFET所需的高电流，并且在MOS模式下提供功率MOSFET栅极之间的电源电压和接地之间的全面切换。

    METHOD AND DEVICE FOR SENDING AND RECEIVING SERVICE DATA
    47.
    发明申请
    METHOD AND DEVICE FOR SENDING AND RECEIVING SERVICE DATA 审中-公开
    用于发送和接收服务数据的方法和设备

    公开(公告)号：US20110318001A1

    公开(公告)日：2011-12-29

    申请号：US13226232

    申请日：2011-09-06

    申请人： Kun Li ,  Jianlin Zhou ,  Yang Cao ,  Xing Hu ,  Jun Cai ,  Xinhua Xiao

    发明人： Kun Li ,  Jianlin Zhou ,  Yang Cao ,  Xing Hu ,  Jun Cai ,  Xinhua Xiao

    IPC分类号： H04J14/00

    CPC分类号： H04J3/1652 ,  H04L49/25

    摘要： In the field of communications technologies, a method and device for sending and receiving service data provided by embodiments of the present invention may be capable of solving the problem that a network system cannot bear a service of arbitrary rate. The method for sending service data includes: receiving at least one flexible data channel to which service data is adapted; searching for an address of a destination port corresponding to a source port of the at least one flexible data channel; scheduling the at least one flexible data channel to an Optical Channel Data Unit-k (ODUk) frame in the corresponding destination port respectively according to channel indication information corresponding to the at least one flexible data channel; and forwarding the ODUk frame to the destination address through an Optical Transport Network (OTN) line after completing construction of the ODUk frame. The embodiments of the present application are applicable to optical network communications.

    摘要翻译： 在通信技术领域中，本发明实施例提供的用于发送和接收业务数据的方法和装置可以解决网络系统不能承受任意速率业务的问题。 用于发送服务数据的方法包括：接收适于服务数据的至少一个灵活数据信道; 搜索与所述至少一个灵活数据信道的源端口对应的目的地端口的地址; 根据对应于所述至少一个灵活数据信道的信道指示信息，将所述至少一个灵活数据信道调度到相应目的地端口中的光信道数据单元k（ODUk）帧; 并在完成ODUk帧的构建之后，通过光传送网（OTN）线路将ODUk帧转发到目的地址。 本申请的实施例可应用于光网络通信。

    LDMOS devices with improved architectures
    49.
    发明授权
    LDMOS devices with improved architectures 有权
    具有改进架构的LDMOS器件

    公开(公告)号：US07977715B2

    公开(公告)日：2011-07-12

    申请号：US12049788

    申请日：2008-03-17

    申请人： Jun Cai

    发明人： Jun Cai

    IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/336

    CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/7816

    摘要： An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.

    摘要翻译： LDMOS器件包括第一导电类型的衬底，衬底上的外延层，在外延层的下部中具有与第一导电类型相反的第二导电类型的掩埋阱，外延层具有第一导电性 在埋层以下。 该器件还包括位于漏极和栅极氧化物上的栅极之间的场氧化物，以及在掩埋阱上方的外延层中具有第二导电类型的鞍形垂直掺杂梯度的源，使得外延中的掺杂剂浓度 在掩埋阱之上和场氧化物的中心部分之下的层低于最靠近漏极和最靠近栅极的场氧化物边缘处的掺杂剂浓度。

    INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS
    50.
    发明申请
    INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS 有权
    集成补充低电压RF-LDMOS

    公开(公告)号：US20110104861A1

    公开(公告)日：2011-05-05

    申请号：US13005593

    申请日：2011-01-13

    申请人： Jun Cai

    发明人： Jun Cai

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7835

    摘要： Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

    摘要翻译： 互补RF LDMOS晶体管在分隔栅极氧化物上具有栅电极。 第二导电类型的源间隔物从第一导电类型的源极阱横向延伸到最薄栅极氧化物上方的栅电极的大约边缘。 第一导电类型的主体从源极抽头的大约底部中心延伸到衬底表面，并且位于分裂栅极氧化物的薄部分的大部分之下。 源间隔物大约是栅极侧壁氧化物的长度，并且与栅电极自对准。 身体也与门电极自对准。 漏极由至少一个缓冲区包围，该缓冲区与最厚栅极氧化物上方的栅极电极的另一边缘自对准，并延伸到漏极的下方，并在最厚栅极氧化物下方横向延伸。 源极漏极和漏极都与栅极侧壁氧化物自对准，从而与栅电极横向间隔开。