公开(公告)号：US08719464B2

公开(公告)日：2014-05-06

申请号：US13308211

申请日：2011-11-30

申请人： Andrew Kegel ,  Mark Hummel ,  Anthony Asaro ,  Phillip Ng

发明人： Andrew Kegel ,  Mark Hummel ,  Anthony Asaro ,  Phillip Ng

IPC分类号： G06F13/28 ,  G06F21/00

CPC分类号： G06F13/28

摘要： The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.

摘要翻译： 本系统使得能够通过输入/输出存储器管理单元（IOMMU）将与访问存储器中的数据相关联的指针传递到输入/输出（I / O）设备。 I / O设备通过IOMMU访问存储器中的数据，而不将数据复制到本地I / O设备存储器中。 I / O设备可以基于指针对存储器中的数据执行操作，使得I / O设备访问存储器而不需要昂贵的副本。

公开(公告)号：US20140052808A1

公开(公告)日：2014-02-20

申请号：US13589463

申请日：2012-08-20

申请人： Venkata S. Krishnan ,  Mark Hummel ,  David E. Mayhew

发明人： Venkata S. Krishnan ,  Mark Hummel ,  David E. Mayhew

IPC分类号： G06F15/167

CPC分类号： H04L67/40

摘要： Described are a system and method for lossless message delivery between two processing devices. Each device includes a remote direct memory access (RDMA) messaging interface. The RDMA messaging interface at the first device generates one or more messages that are processed by the RDMA messaging interface of the second device. The RDMA messaging interface of the first device outputs a notification to the second device that a message of the one or more messages is available at the first device. A determination is made that the second device has resources to accommodate the message. The second device performs an operation in response to determining that the processing device has the resources to accommodate the message.

摘要翻译： 描述了用于两个处理设备之间无损消息传递的系统和方法。 每个设备包括远程直接内存访问（RDMA）消息接口。 第一设备上的RDMA消息接口生成由第二设备的RDMA消息接发处理的一个或多个消息。 第一设备的RDMA消息接口向第二设备输出一个或多个消息的消息在第一设备可用的通知。 确定第二设备具有容纳消息的资源。 第二装置响应于确定处理装置具有容纳消息的资源而执行操作。

公开(公告)号：US20130346531A1

公开(公告)日：2013-12-26

申请号：US13531890

申请日：2012-06-25

申请人： Mark Hummel ,  David E. Mayhew ,  Michael J. Osborn ,  Anton Chernoff ,  Venkata S. Krishnan

发明人： Mark Hummel ,  David E. Mayhew ,  Michael J. Osborn ,  Anton Chernoff ,  Venkata S. Krishnan

IPC分类号： H04L12/56 ,  H04L12/28 ,  G06F15/167 ,  H04L12/66

CPC分类号： H04L12/00 ,  G06F13/4022 ,  G06F2213/0058 ,  G06F2213/3808 ,  H04L49/70 ,  H04Q1/00 ,  H04Q3/00 ,  H04W76/00 ,  Y02D10/14 ,  Y02D10/151

摘要： Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

摘要翻译： 描述了包括多个虚拟网络接口卡（vNIC）和输入/输出（I / O）处理复合体的聚合设备。 vNIC与多个处理设备通信。 每个处理设备具有至少一个虚拟机（VM）。 I / O处理复合体位于vNIC和至少一个物理网卡之间。 I / O处理复合体包括至少一个代理NIC和虚拟交换机。 虚拟交换机通过由至少一个VM和至少一个代理NIC之间的多个vNIC的vNIC建立的通信路径与多个处理设备的处理设备交换数据。

公开(公告)号：US20130339466A1

公开(公告)日：2013-12-19

申请号：US13526973

申请日：2012-06-19

申请人： David E. Mayhew ,  Mark Hummel ,  Michael J. Osborn

发明人： David E. Mayhew ,  Mark Hummel ,  Michael J. Osborn

IPC分类号： G06F15/167

CPC分类号： G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  H04L49/103

摘要： Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

摘要翻译： 描述了用于互连服务器节点的聚合设备和方法。 聚合设备可以包括输入区域，输出区域和存储器开关。 输入区域包括多个输入端口。 存储器开关具有耦合到输入端口的共享的硅通孔（TSV）存储器，用于临时存储在来自多个源装置的输入端口接收的数据。 输出区域包括耦合到TSV存储器的多个输出端口。 输出端口将数据提供给多个目标设备。 存储器分配系统协调从源设备到TSV存储器的数据传输。 输出端口接收和处理来自TSV存储器的数据，而与输入端口的通信无关。

公开(公告)号：US20130166834A1

公开(公告)日：2013-06-27

申请号：US13332853

申请日：2011-12-21

申请人： David E. Mayhew ,  Mark Hummel

发明人： David E. Mayhew ,  Mark Hummel

IPC分类号： G06F12/10 ,  G06F12/02

CPC分类号： G06F12/12 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/2024 ,  G06F2212/652 ,  G06F2212/684

摘要： A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.

摘要翻译： 用于管理虚拟地址以进行物理地址转换的方法和装置利用子页级别的故障检测和访问。 该方法和装置还可以使用附加的子页面和页面存储非易失性存储（NVS）。 该方法和装置确定页面故障是否发生或是否发生子页面故障以实现地址转换，并且还操作使得如果发生子页面故障，则将从NVS到DRAM的对应于故障的子页面加载到诸如 DRAM或历史上称为主存储器的任何其它合适的易失性存储器。 如果发生页面错误，则该方法和装置在没有操作系统帮助的情况下确定页面错误是否发生，并且是将来自NVS的故障页面加载到DRAM的硬件页面故障检测系统。

公开(公告)号：US20120246381A1

公开(公告)日：2012-09-27

申请号：US13309750

申请日：2011-12-02

申请人： Andy Kegel ,  Mark Hummel ,  Steve Glaser ,  Tony Asaro ,  Philip NG ,  Jeffrey Cheng

发明人： Andy Kegel ,  Mark Hummel ,  Steve Glaser ,  Tony Asaro ,  Philip NG ,  Jeffrey Cheng

IPC分类号： G06F12/10

CPC分类号： G06F12/109 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/151 ,  G06F2212/651

摘要： Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

摘要翻译： 本发明的实施例提供了用于I / O设备的存储器地址转换的上下文中的输入输出存储器管理单元（IOMMU）双层寻址的方法，系统和计算机可读介质。 根据实施例，一种方法包括根据与与I / O相关联的地址转换事务相关联的进程地址空间标识符，使用访客地址转换表将访客虚拟地址（GVA）翻译成相应的客体物理地址（GPA） 设备，并且根据与地址转换事务相关联的设备标识符，使用系统地址转换表将GPA转换为相应的系统物理地址（SPA）。

公开(公告)号：US20070038840A1

公开(公告)日：2007-02-15

申请号：US11503391

申请日：2006-08-11

申请人： Mark Hummel ,  Andrew Lueck ,  Geoffrey Strongin ,  Mitchell Alsup ,  Michael Haertel

发明人： Mark Hummel ,  Andrew Lueck ,  Geoffrey Strongin ,  Mitchell Alsup ,  Michael Haertel

IPC分类号： G06F12/00

CPC分类号： G06F12/1081 ,  G06F12/1027 ,  G06F2212/683

摘要： In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion wait command by delaying completion of the completion wait command until: (1) a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands is received; and (2) the control unit transmits one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system and has become visible to the system.

摘要翻译： 在一个实施例中，输入/输出存储器管理单元（IOMMU）被配置为接收定义的完成等待命令，以在完成等待命令完成之前确保由IOMMU完成一个或多个以前的无效命令。 IOMMU被配置为通过延迟完成等待命令的完成来响应完成等待命令，直到：（1）接收与取决于由前述无效命令无效的转换条目的每个未完成存储器读操作对应的读响应 ; （2）控制单元向上游发送一个或多个操作，以确保依赖于由前述无效命令无效的转换表项的每个存储器写入操作至少达到计算机系统中的相干结构的桥接，以及 已经变得对系统可见。