公开(公告)号：US12273122B2

公开(公告)日：2025-04-08

申请号：US18129109

申请日：2023-03-31

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang

IPC: H03M1/12 ,  H03M1/06

Abstract: A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.

公开(公告)号：US12212332B2

公开(公告)日：2025-01-28

申请号：US18105675

申请日：2023-02-03

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Shih-Hsiung Huang ,  Liang-Wei Huang

IPC: H03M1/10 ,  H03M1/06

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit. The echo calibration circuit makes response coefficients converge according to the error signal and pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates codeword offset table according to the offset.

公开(公告)号：US12143118B2

公开(公告)日：2024-11-12

申请号：US17864471

申请日：2022-07-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Yen-Ting Wu ,  Wei-Cian Hong

IPC: H03M1/12

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.

公开(公告)号：US12107597B2

公开(公告)日：2024-10-01

申请号：US17857621

申请日：2022-07-05

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong ,  Sheng-Yen Shih

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/468 ,  H03M1/1245

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

公开(公告)号：US11923866B2

公开(公告)日：2024-03-05

申请号：US17683397

申请日：2022-03-01

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Shih-Hsiung Huang ,  Liang-Wei Huang

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

公开(公告)号：US11784654B2

公开(公告)日：2023-10-10

申请号：US17691502

申请日：2022-03-10

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Shih-Hsiung Huang ,  Liang-Wei Huang

IPC: H03M1/10 ,  H03M7/00 ,  H03M1/66

CPC classification number: H03M1/1009 ,  H03M1/1071 ,  H03M1/10 ,  H03M1/66 ,  H03M7/00

Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

公开(公告)号：US11671107B2

公开(公告)日：2023-06-06

申请号：US17388756

申请日：2021-07-29

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1023 ,  H03M1/466

Abstract: An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.

公开(公告)号：US11476864B2

公开(公告)日：2022-10-18

申请号：US17410382

申请日：2021-08-24

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Pan Zhang ,  Kai-Yin Liu ,  Shih-Hsiung Huang ,  Wei-Jyun Wang

IPC: H03M1/38 ,  H03M1/16 ,  H03M1/46 ,  H03M1/10 ,  H03M1/80 ,  H03M1/12 ,  H03M1/44

Abstract: A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

公开(公告)号：US11456767B2

公开(公告)日：2022-09-27

申请号：US17209575

申请日：2021-03-23

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Chi-Sheng Hsu ,  Yan-Guei Chen ,  Shih-Hsiung Huang ,  Liang-Wei Huang

IPC: H04B1/12 ,  H04B1/10 ,  H03G3/30 ,  H04B1/16

Abstract: A method for receiving data includes receiving a transmission signal through a channel, adjusting the intensity of the transmission signal to generate an adjusted transmission signal according to an analog gain level, converting the adjusted transmission signal into a digital signal, filtering the digital signal to generate a filtered signal according to a set of filter coefficients, and adjusting intensity of the filtered signal according to a digital gain level. The method further includes, in a training mode, estimating a transmission condition of the channel and adjusting the analog gain level and the digital gain level according to the transmission condition for obtaining convergent values for the set of filter coefficients before the training mode ends, and in a data mode, performing a gain adjustment operation to adjust the analog gain level and to adjust the digital gain level according to the adjustment made to the analog gain level.

公开(公告)号：US11456752B2

公开(公告)日：2022-09-27

申请号：US17408524

申请日：2021-08-23

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46

Abstract: A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.