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公开(公告)号：US12191873B2
公开(公告)日：2025-01-07
申请号：US18087469
申请日：2022-12-22
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Hsuan-Ting Ho , Shih-Hsiung Huang , Liang-Wei Huang
Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients. A current calculating circuit generates converged coefficients statistics values and perform calculation thereon with a predetermined inverse matrix to generate a current amount of each of the thermo-controlled current sources. An error calculation circuit subtracts the echo signal and the echo-canceling signal to generate the error signal.
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公开(公告)号：US12184170B2
公开(公告)日：2024-12-31
申请号：US18086720
申请日：2022-12-22
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang , Wei-Cian Hong
Abstract: A comparator-based switched-capacitor circuit has a first output terminal and a second output terminal, and includes a switch-capacitor network, a first current source, and a second current source. Each of the first current source and the second current source includes a first transistor, a second transistor, a capacitor, and a buffer circuit. The first transistor has a first source, a first drain, and a first gate. The first drain is coupled to the first output terminal, the first source is coupled to a reference voltage, and the first gate is coupled to the switch-capacitor network. The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.
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公开(公告)号：US11567522B2
公开(公告)日：2023-01-31
申请号：US17405380
申请日：2021-08-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Che-Wei Chang , Kai-Yin Liu , Liang-Huan Lei , Shih-Hsiung Huang
Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.
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公开(公告)号：US11418206B2
公开(公告)日：2022-08-16
申请号：US17333063
申请日：2021-05-28
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang , Ying-Cheng Wu , Chien-Ming Wu , Kai-Yin Liu
Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.
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5.发明授权公开(公告)号：US10693487B1
公开(公告)日：2020-06-23
申请号：US16574742
申请日：2019-09-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei , Shih-Hsiung Huang
IPC: H03M1/46
Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.
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Patent Agency Ranking
公开(公告)号：US10587279B1
公开(公告)日：2020-03-10
申请号：US16385182
申请日：2019-04-16
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chieh Yang , Shih-Hsiung Huang , Liang-Huan Lei
Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
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公开(公告)号：US10312925B1
公开(公告)日：2019-06-04
申请号：US16105142
申请日：2018-08-20
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chih-Lung Chen , Ying-Cheng Wu , Shih-Hsiung Huang
Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
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公开(公告)号：US12143117B2
公开(公告)日：2024-11-12
申请号：US17870983
申请日：2022-07-22
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang
Abstract: A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion. The encoder circuit generates a digital output according to a corresponding coarse digital code and the fine digital code.
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公开(公告)号：US12113544B2
公开(公告)日：2024-10-08
申请号：US17864464
申请日：2022-07-14
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Sheng-Yen Shih , Shih-Hsiung Huang , Wei-Cian Hong
CPC classification number: H03M1/38 , H03M1/1245 , H03M3/04
Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.
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公开(公告)号：US12068755B2
公开(公告)日：2024-08-20
申请号：US17944340
申请日：2022-09-14
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang , Wei-Cian Hong , Sheng-Yen Shih
Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.
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