Nanotube tip for atomic force microscope
    41.
    发明授权
    Nanotube tip for atomic force microscope 失效
    纳米管尖端用于原子力显微镜

    公开(公告)号:US06780664B1

    公开(公告)日:2004-08-24

    申请号:US10324327

    申请日:2002-12-20

    IPC分类号: H01L2100

    摘要: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.

    摘要翻译: 提供了各种显微镜探针及其制造方法。 一方面,提供一种制造显微镜探针的方法,其包括提供构件并在构件上形成第一膜。 当暴露于含碳化合物时,第一种膜促进碳纳米管的生长。 在第一膜上形成第二膜。 第二膜在其中具有露出第一膜的一部分的开口。 在第一膜的暴露部分上形成碳纳米管。

    Data processing device test apparatus and method therefor
    42.
    发明授权
    Data processing device test apparatus and method therefor 失效
    数据处理装置试验装置及其方法

    公开(公告)号:US06546513B1

    公开(公告)日:2003-04-08

    申请号:US09586572

    申请日:2000-06-02

    IPC分类号: G01R3128

    CPC分类号: G06F11/263 G01R31/307

    摘要: A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT). The overlaid image provides a visual correlation of the failure with the structural elements of the DUT at the level of resolution of the microscope itself.

    摘要翻译: 实现了用于测试数据处理设备的方法和设备机制。 测试机制通过将扫描显微镜图像与选定的速度路径故障相关联来隔离关键路径。 在每个图案向量的开始处产生具有预选值的触发信号。 扫描显微镜的扫描由计算机控制,计算机还接收并处理从显微镜返回的图像信号。 触发信号的值与在DUT上驱动的一组图案线相关。 根据模式线路故障的检测和失败的特定线路,触发器被断言或否定。 响应于特征的特定速度路径故障的检测和触发信号,控制计算机覆盖被测器件(DUT)的图像上的掩模。 重叠的图像在显微镜本身的分辨率水平下提供了故障与DUT的结构元件的视觉相关性。

    Silicon photon detector
    43.
    发明授权
    Silicon photon detector 有权
    硅光子探测器

    公开(公告)号:US08232586B2

    公开(公告)日:2012-07-31

    申请号:US12539821

    申请日:2009-08-12

    IPC分类号: H01L31/101

    CPC分类号: H01L31/113

    摘要: A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.

    摘要翻译: 提供硅光子检测器装置和方法,用于在部分耗尽的浮体SOI场效应晶体管(310)中检测入射光子,该场效应晶体管(310)在硅光子检测器(310)捕获由浮动体区域(304)中的可见光和中红外光产生的电荷 被配置在检测模式中,然后在读取模式下用电流检测器测量或读取所得到的增强的漏极电流。

    Electrical probing of SOI circuits
    44.
    发明授权
    Electrical probing of SOI circuits 有权
    SOI电路的电探测

    公开(公告)号:US07235800B1

    公开(公告)日:2007-06-26

    申请号:US09583617

    申请日:2000-05-31

    IPC分类号: G01R31/305 G01R31/02

    CPC分类号: G01R31/307

    摘要: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching or needing to breach the thin insulator layer of the SOI structure. According to an example embodiment of the present invention, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. An exposed region is formed where the substrate has been removed. A detectable response from the exposed region is induced, for example, by an electron beam, as a function of a portion of the active circuitry within the die.

    摘要翻译: 具有绝缘体上硅(SOI)结构的半导体管芯的分析通过从背面访问管芯内的电路而不必破坏或需要破坏SOI结构的薄绝缘体来增强。 根据本发明的示例性实施例,从电路侧的具有SOI结构和背面相反电路的半导体管芯的背面去除衬底的一部分。 在衬底被去除的地方形成曝光区域。 来自暴露区域的可检测的响应例如通过电子束被引发,作为管芯内有源电路的一部分的函数。

    Circuit analysis and manufacture using electric field-induced effects
    45.
    发明授权
    Circuit analysis and manufacture using electric field-induced effects 失效
    电路分析和制造采用电场效应

    公开(公告)号:US06894518B1

    公开(公告)日:2005-05-17

    申请号:US10113780

    申请日:2002-03-29

    IPC分类号: G01R31/311 G01R31/26

    CPC分类号: G01R31/311

    摘要: Circuitry within a semiconductor die is analyzed by applying an electric field without necessarily directly accessing the circuitry. According to an example embodiment of the present invention, an electric field is applied to a semiconductor die and used to stimulate circuitry therein. A photoemission response of the die to the electric field is detected and used to detect an electrical characteristic of the die. This is particularly useful in applications where it is desired to direct stimulation to the die from an external source and to also externally detect a response of the die to the stimulation. In this manner, the die can be tested without necessarily directly contacting the die and, when the electric field is applied in a scanning mode over the die, can be effected without necessarily knowing the location of a defect in the die.

    摘要翻译: 通过施加电场来分析半导体管芯内的电路,而不必直接访问电路。 根据本发明的示例性实施例,电场被施加到半导体管芯并且用于在其中刺激电路。 检测芯片对电场的光电子发射响应并用于检测管芯的电特性。 这尤其适用于需要从外部源引导模头的刺激并且还从外部检测模具对刺激的反应的应用中。 以这种方式,可以测试管芯而不必直接接触管芯,并且当以扫描模式在管芯上施加电场时,可以不必知道管芯中缺陷的位置而进行。

    Optical analysis for SOI integrated circuits
    46.
    发明授权
    Optical analysis for SOI integrated circuits 失效
    SOI集成电路的光学分析

    公开(公告)号:US06716683B1

    公开(公告)日:2004-04-06

    申请号:US09887638

    申请日:2001-06-22

    IPC分类号: H01L2100

    CPC分类号: G01R31/311 G01N21/66

    摘要: An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that enhances the ability to detect photoemissions from the die. According to an example embodiment of the present invention, one of two or more lenses having a higher relative photon count is identified and used to analyze a semiconductor die. The die has at least a portion of the insulator of the SOI structure exposed, and photon emissions are detected using each lens via the exposed insulator in response to the die being stimulated. The number of photons detected using each lens is compared, and the lens having a higher photon count rate is identified, optimizing the photon count for the particular type of die preparation used to expose the insulator. The identified lens is then used with the high-speed detector to detect photoemissions from the die, and the detected photoemissions are used to analyze the die.

    摘要翻译: 分析具有绝缘体上硅(SOI)结构的集成电路芯片,以提高从模具检测光电发射的能力。 根据本发明的示例性实施例,识别出具有较高相对光子计数的两个或更多个透镜中的一个,并用于分析半导体管芯。 裸片具有暴露的SOI结构的绝缘体的至少一部分,并且响应于被激励的裸片,经由暴露的绝缘体使用每个透镜来检测光子发射。 比较使用每个透镜检测的光子的数量,并且识别具有较高光子计数率的透镜,优化用于暴露绝缘体的特定类型的模具制备的光子计数。 然后将识别的透镜与高速检测器一起使用以检测来自管芯的光电发射,并且使用检测到的光电管来分析管芯。

    IC analysis involving logic state mapping in a SOI die
    47.
    发明授权
    IC analysis involving logic state mapping in a SOI die 失效
    IC分析涉及SOI芯片中的逻辑状态映射

    公开(公告)号:US06653849B1

    公开(公告)日:2003-11-25

    申请号:US09864708

    申请日:2001-05-23

    IPC分类号: G01R3102

    摘要: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the hack side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement from the die that is used for analysis.

    摘要翻译: 通过从背面访问管芯内的电路而不破坏SOI结构的薄绝缘体层来增强具有绝缘体上硅(SOI)结构的半导体管芯的分析。 根据示例性实施例,从电路侧具有SOI结构和背面相对电路的半导体芯片的背面侧去除衬底的一部分。 通过电容耦合装置对管芯内的电路的一部分进行电连接。 电气连接用于从用于分析的管芯获得电气测量。

    Single point high resolution time resolved photoemission microscopy system and method
    48.
    发明授权
    Single point high resolution time resolved photoemission microscopy system and method 有权
    单点高分辨率时间分辨光电子显微镜系统及方法

    公开(公告)号:US06608494B1

    公开(公告)日:2003-08-19

    申请号:US09205589

    申请日:1998-12-04

    IPC分类号: G01R31302

    CPC分类号: G01R31/311 G01R31/303

    摘要: A method and system providing single point high spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A photo-diode optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

    摘要翻译: 一种为集成电路的光电显微镜提供单点高空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路,并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

    Resistivity analysis
    49.
    发明授权
    Resistivity analysis 有权
    电阻率分析

    公开(公告)号:US07062399B1

    公开(公告)日:2006-06-13

    申请号:US09586518

    申请日:2000-06-02

    IPC分类号: G01R31/14

    CPC分类号: G01R31/2875 G01R31/311

    摘要: According to an example embodiment of the present invention a semiconductor die having a resistive electrical connection is analyzed. Heat is directed to the die as the die is undergoing a state-changing operation to cause a failure due to suspect circuitry. The die is monitored, and a circuit path that electrically changes in response to the heat is detected and used to detect that a particular portion therein of the circuit is resistive. In this manner, the detection and localization of a semiconductor die defect that includes a resistive portion of a circuit path is enhanced.

    摘要翻译: 根据本发明的示例性实施例,分析具有电阻电连接的半导体管芯。 当芯片正在进行状态改变操作以引起可疑电路引起的故障时,热量被引导到芯片。 监测管芯,并且检测并响应于热而电变化的电路路径以检测其中电路中的特定部分是电阻性的。 以这种方式,增强了包括电路路径的电阻部分的半导体管芯缺陷的检测和定位。

    Dual-differential interferometry for silicon device damage detection
    50.
    发明授权
    Dual-differential interferometry for silicon device damage detection 失效
    用于硅器件损伤检测的双差分干涉测量

    公开(公告)号:US06992773B1

    公开(公告)日:2006-01-31

    申请号:US09386112

    申请日:1999-08-30

    IPC分类号: G01B9/02

    CPC分类号: G01N21/95684

    摘要: According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for detecting a defect in a surface of the die includes directing light through a first beam splitter; directing light of a known wavelength at the beam splitter, wherein the first beam splitter is adapted to direct a first beam of light into the back side of the semiconductor die which reflects a second beam of light back; and redirecting the second beam to a second beam splitter, the second beam splitter generating third and fourth beams of light. Analysis of the third and fourth beams of light is then performed, and this analysis can include using detectors in respective paths of the third and fourth beams of light to generate an arrival time differential and then comparing the differential with a reference previously generated using a nondefective die.

    摘要翻译: 根据本公开的一个方面和针对倒装芯片封装管芯的特定示例应用,用于检测管芯表面中的缺陷的方法包括将光引导通过第一分束器; 将所述已知波长的光导向所述分束器,其中所述第一分束器适于将第一光束引导到所述半导体管芯的反射第二光束的背面; 以及将所述第二光束重定向到第二分束器,所述第二分束器产生第三和第四光束。 然后执行第三和第四光束的分析,并且该分析可以包括在第三和第四光束的相应路径中使用检测器以产生到达时间差,然后将差分与先前使用无缺陷 死。