公开(公告)号：US08488729B1

公开(公告)日：2013-07-16

申请号：US12879706

申请日：2010-09-10

申请人： David W. Mendel ,  Brent A. Fairbanks ,  Ning Xue

发明人： David W. Mendel ,  Brent A. Fairbanks ,  Ning Xue

IPC分类号： H04L7/00

CPC分类号： H04L25/14

摘要： Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit (“IC”) is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned. If not, then data in a lane for which the training pattern ends earliest is delayed by an amount corresponding to the length of one or more cycles of the training pattern.

摘要翻译： 公开了用于对准跨越多个车道的高速数据的方法和结构。 在一个实施例中，提供了一种方法和集成电路（“IC”），用于在数据解扰之前跨多个数据通道接收和对准加扰的训练数据。 在一些实现中，已知的加扰训练模式在每个通道中是不同的，并且对齐包括将每个通道中的输入训练数据与每个通道中的不同已知加扰训练模式进行比较。 在一些实施方式中，在扰频数据对准然后被解扰后，根据已知的未加扰训练模式进行检查，以确保加扰的训练数据的对准是正确的。 在替代实施例中，在对齐数据之前对数据进行解扰，但是对偏移校正电路输出进行监视以确定训练模式是否在跨越正在对准的多个通道的同一时间结束。 如果不是，则训练模式最早结束的车道中的数据被延迟与训练模式的一个或多个周期的长度对应的量。

公开(公告)号：US08001499B1

公开(公告)日：2011-08-16

申请号：US12053481

申请日：2008-03-21

申请人： Greg William Baeckler ,  David W. Mendel ,  Michael D. Hutton

发明人： Greg William Baeckler ,  David W. Mendel ,  Michael D. Hutton

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054

摘要： A pragma is used to pass circuit type information to a Computer Aided design (CAD) tool. The CAD tool then selects an alternate synthesis or timing algorithm based on the circuit type, and a circuit design for use in an electronic device is created. Practical applications include using alternate algorithms specific to different circuit types, such as, Cyclic Redundancy Checks (CRC), bus arbiters, state machine encoders, barrel shifters, preferential cores, and legacy circuits. One embodiment generates informative messages for the designer once the circuit type is known and the analysis is performed. Another embodiment generates pragmas that can be later used by circuit designers in future circuit designs.

摘要翻译： 使用编译指令将电路类型信息传递到计算机辅助设计（CAD）工具。 然后，CAD工具基于电路类型选择替代合成或定时算法，并且创建用于电子设备的电路设计。 实际应用包括使用特定于不同电路类型的替代算法，例如循环冗余校验（CRC），总线仲裁器，状态机编码器，桶形移位器，优先核心和传统电路。 一旦实施了电路类型并且执行了分析，一个实施例为设计者生成信息性消息。 另一个实施例产生可以在将来的电路设计中由电路设计者稍后使用的编译指示。

公开(公告)号：US20090289660A1

公开(公告)日：2009-11-26

申请号：US12356317

申请日：2009-01-20

申请人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

发明人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

摘要翻译： 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：US07249329B1

公开(公告)日：2007-07-24

申请号：US10859325

申请日：2004-06-01

申请人： Gregg William Baeckler ,  Jinyong Yuan ,  David W. Mendel

发明人： Gregg William Baeckler ,  Jinyong Yuan ,  David W. Mendel

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/505 ,  Y02T10/82

摘要： Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.

摘要翻译： 提供了用于确定是否可以使用不完整查找表（LUT）来实现功能的技术映射技术。 例如，将函数的输出与功能输入信号的每个二进制值的不完整LUT的输出以及存储在不完全LUT中的位的每个二进制值进行比较。 对于功能不对称的LUT，相对于LUT的输入端，可以重复进行输入信号的多个排列的处理。 作为另一示例，用户功能被转换为多路复用器和完整LUT的网络，其被分析以确定不完整的LUT是否可以实现该功能。 作为另一示例，为功能构建真值表。 然后，将真值表变量逐个测试作为每个输入位置的候选，使用协同因子和依赖性检查。

公开(公告)号：US06320411B1

公开(公告)日：2001-11-20

申请号：US09443969

申请日：1999-11-19

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

公开(公告)号：US06275065B1

公开(公告)日：2001-08-14

申请号：US09479405

申请日：2000-01-06

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

摘要： A logic element for a programmable logic device to implement a lonely register architecture. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 用于可编程逻辑器件实现孤独寄存器架构的逻辑元件。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US06246260B1

公开(公告)日：2001-06-12

申请号：US09371440

申请日：1999-08-10

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 可编程逻辑器件的逻辑元件，用于实现全局共享扩展器。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US06184710B2

公开(公告)日：2001-02-06

申请号：US08924768

申请日：1997-08-27

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

摘要翻译： 可编程逻辑器件具有可编程逻辑的多个区域和用于向各区域之间和之间输送信号的通用互连网络。 除了通用互连网络之外，从每个区域的输出到一个或多个其他相邻或附近区域的输入提供更直接的互连。 这些直接互连中的至少一些优选地与更常规的输入复用到其他区域，使得每个区域所需的输入资源不会变得过大。 本发明对于使用产品总和（“Pterm”）逻辑执行基本逻辑的装置特别有用。 然而，本发明在诸如使用查找表执行基本逻辑的那些装置中也是有用的。

公开(公告)号：US5986465A

公开(公告)日：1999-11-16

申请号：US835557

申请日：1997-04-08

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 可编程逻辑器件的逻辑元件，用于实现全局共享扩展器。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US5341308A

公开(公告)日：1994-08-23

申请号：US702001

申请日：1991-05-17

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5072

摘要： Circuit partitioning methods are enhanced by more accurately accounting for circuit nets which include connections external to the circuit being partitioned. The user can also prohibit movement of any circuit element or cell which the user does not want to have moved. The user can also prevent splitting of any net or set of cells which the user does not want to have split. The balance requirement of prior art methods is modified to allow circuit element moves which imbalance the partition. However, balance is ultimately restored by further circuit element moves.

摘要翻译： 通过更精确地计算包括被分割的电路外部的连接的电路网来增强电路划分方法。 用户还可以禁止用户不想移动的任何电路元件或单元的移动。 用户还可以防止用户不想拆分的任何网络或单元格的分割。 对现有技术方法的平衡要求进行了修改，以允许不均衡隔板的电路元件移动。 然而，通过进一步的电路元件移动最终还原平衡。