公开(公告)号：US08786057B2

公开(公告)日：2014-07-22

申请号：US12178495

申请日：2008-07-23

申请人： Tsu-Jae King ,  Victor Moroz

发明人： Tsu-Jae King ,  Victor Moroz

IPC分类号： H01L29/06

CPC分类号： H01L29/34 ,  H01L21/78 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L2223/5446 ,  Y10S438/974

摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

摘要翻译： 通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管， 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

公开(公告)号：US07266010B2

公开(公告)日：2007-09-04

申请号：US11288883

申请日：2005-11-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/00

CPC分类号： G11C11/005 ,  G11C13/0011 ,  G11C14/009

摘要： A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such as a 3T, negative differential resistance (NDR) transistor-based circuit, or a 6T (conventional SRAM) circuit. The programmable resistor can be formed in a metal layer above the SRAM circuit to minimize the area requirements for the memory cell. Just before shutdown of the SRAM cell, the resistance state of the programmable resistor is changed (if necessary) based on the data value stored at the storage node. The programmable resistor provides a non-volatile indication of the stored data value at the time of power off. Then, when power is restored to the SRAM cell, a data value based on the resistance state of the programmable resistor is written back into the SRAM circuit.

摘要翻译： 静态随机存取存储器（SRAM）单元包括连接到SRAM电路的存储节点的SRAM电路和可编程电阻器。 SRAM电路可以是任何类型的SRAM电路，例如3T，负差分电阻（NDR）晶体管电路或6T（常规SRAM）电路）。 可编程电阻器可以形成在SRAM电路上方的金属层中，以最小化存储单元的面积要求。 在SRAM单元关闭之前，可编程电阻器的电阻状态根据存储在存储节点上的数据值而变化（如果需要）。 可编程电阻器在断电时提供存储的数据值的非易失性指示。 然后，当电源恢复到SRAM单元时，基于可编程电阻器的电阻状态的数据值被写回SRAM电路。

公开(公告)号：US20070121371A1

公开(公告)日：2007-05-31

申请号：US11288883

申请日：2005-11-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/00

CPC分类号： G11C11/005 ,  G11C13/0011 ,  G11C14/009

摘要： A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such as a 3T, negative differential resistance (NDR) transistor-based circuit, or a 6T (conventional SRAM) circuit. The programmable resistor can be formed in a metal layer above the SRAM circuit to minimize the area requirements for the memory cell. Just before shutdown of the SRAM cell, the resistance state of the programmable resistor is changed (if necessary) based on the data value stored at the storage node. The programmable resistor provides a non-volatile indication of the stored data value at the time of power off. Then, when power is restored to the SRAM cell, a data value based on the resistance state of the programmable resistor is written back into the SRAM circuit.

公开(公告)号：US07220636B2

公开(公告)日：2007-05-22

申请号：US10982425

申请日：2004-11-04

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/20

CPC分类号： H01L21/28185 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.

摘要翻译： 公开了用于控制NDR元件的NDR特性的各种过程，例如峰 - 谷比（PVR），NDR起始电压（V NDR N）和相关参数。 这些过程基于常规的半导体制造操作，使得可以使用基于硅的衬底以及其他类型的器件来制造NDR器件。

公开(公告)号：US07186621B2

公开(公告)日：2007-03-06

申请号：US11045539

申请日：2005-01-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/8234

CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/823462 ,  H01L29/42332

摘要： A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.

摘要翻译： 公开了一种使用常规MOS制造操作在硅基衬底上形成的负差动电阻（NDR）场效应晶体管元件。 还公开了用于改善NDR元件的各种NDR特性的方法，例如峰 - 谷比（PVR），NDR起始电压（V NDR N）和相关参数。

公开(公告)号：US07109078B2

公开(公告)日：2006-09-19

申请号：US10754229

申请日：2004-01-08

申请人： Tsu-Jae King ,  David K. Y. Liu

发明人： Tsu-Jae King ,  David K. Y. Liu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7881 ,  G11C5/142 ,  H01L29/788 ,  H01L29/792

摘要： A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that uses charge trapping for altering channel conductivity characteristics is disclosed. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the charge trapping device so that the entire process is compatible and achieved with CMOS processing techniques, and so that non-charge trapping devices can be formed at the same time in a common sequence of manufacturing operations.

摘要翻译： 公开了一种制造使用电荷捕获来改变沟道电导特性的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）的方法。 使用其它合适的和常规的处理步骤来最终完成电荷俘获装置的制造，使得整个过程与CMOS处理技术相兼容并且实现，并且使得非电荷捕获装置可以同时形成在 常见的制造操作顺序。

公开(公告)号：US07098472B2

公开(公告)日：2006-08-29

申请号：US11229182

申请日：2005-09-15

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L31/0336

CPC分类号： G11C11/39 ,  G11C11/417

摘要： A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.

摘要翻译： 可以通过耦合具有NDR的FET的栅极和漏极来形成双端子NDR器件，使得耦合的栅极和漏极形成第一端子，并且NDR功能FET的源极形成第二端子。 通过在以这种方式配置的具有NDR功能的FET的主体和源极之间施加适当的体偏置，可以强制使具有NDR功能的FET以负阈值电压工作，从而允许所得到的双端器件展现出期望的 NDR特性。 例如，该双端器件可以用作静态随机存取存储器（SRAM）单元中的负载元件以及器件的NDR特性将是有益的各种其它电路。

公开(公告)号：US07060524B2

公开(公告)日：2006-06-13

申请号：US10966575

申请日：2004-10-15

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/00

CPC分类号： H01L21/28185 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/78

摘要： A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.

摘要翻译： 公开了一种测量/强调诸如负差分电阻（NDR）FET的电荷俘获装置的方法。 通过在制造期间/之后操作/强调电荷陷阱装置，可以有利地改变电荷陷阱的分布以改善性能。

公开(公告)号：US20060028881A1

公开(公告)日：2006-02-09

申请号：US11243346

申请日：2005-10-03

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C7/10 ,  G11C11/00

CPC分类号： G11C11/39 ,  G11C11/413

摘要： Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store operations to reduce power dissipation and improve reliability. Latch strength can also be increased to improve read speed, while latch strength can be reduced to improve write speed. In an SRAM cell including at least a negative differential resistance (NDR) device as a pull-up element, this type of latch control can be achieved through appropriate biasing of the NDR device(s). For example, drain-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength. Similarly, gate-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength.

摘要翻译： 通过使用适当的锁定强度控制，可以增强静态随机存取存储器（SRAM）性能。 例如，SRAM单元中的锁存强度在数据存储操作期间增加，以减少功耗并提高可靠性。 也可以提高锁存强度，以提高读取速度，同时可以降低锁定强度，提高写入速度。 在至少包括作为上拉元件的负差分电阻（NDR）装置的SRAM单元中，可以通过NDR器件的适当偏置来实现这种类型的锁存控制。 例如，漏极 - 源极偏压可分别增加或减小以分别提高或降低锁定强度。 类似地，栅极到源极偏置可以分别增加或减小以分别提高或降低闩锁强度。

公开(公告)号：US20060007773A1

公开(公告)日：2006-01-12

申请号：US11229182

申请日：2005-09-15

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C8/02

CPC分类号： G11C11/39 ,  G11C11/417

摘要： A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.