公开(公告)号：US20210304737A1

公开(公告)日：2021-09-30

申请号：US17189710

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwoo HAN ,  Kwangyoun KIM ,  Chanwoo KIM ,  Kyungmin LEE ,  Youngho HAN

IPC: G10L15/18 ,  G10L15/06 ,  G10L15/26

Abstract: Disclosed are an electronic device and a method of controlling the electronic device. An electronic device according to an embodiment may perform a method comprising: performing natural language understanding for a first text included in learning data, obtaining first information associated with a speech corresponding to the first text being uttered based on a result of the natural language understanding, obtain second information associated with an acoustic feature corresponding to the speech corresponding to the first text being uttered based on the first information, obtaining a plurality of speech signals corresponding to the first text by converting a first speech signal corresponding to the first text based on the first information and the second information, and training a speech recognition model based on the plurality of obtained speech signals and the first text.

公开(公告)号：US20210111724A1

公开(公告)日：2021-04-15

申请号：US17006152

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong JUNG ,  Sangdon JUNG ,  Kyungmin LEE ,  Byungki HAN

IPC: H03L7/081 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091

Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

公开(公告)号：US20210036550A1

公开(公告)日：2021-02-04

申请号：US16929581

申请日：2020-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mincheol HA ,  Kwangseob KIM ,  Kihyun KIM ,  Dongzo KIM ,  Jihye KIM ,  Yunjeong NOH ,  Changhak O ,  Kyungmin LEE ,  Hyungkoo CHUNG

IPC: H02J50/10 ,  H02J7/02 ,  H02J50/80

Abstract: An electronic device according to an embodiment may include: a wireless charging coil; a power transmission circuit configured to be electrically connected to the wireless charging coil; a wireless communication circuit configured to communicate with an external electronic device; and a control circuit. The control circuit may be configured to: transmit power to an external electronic device; obtain data corresponding to power received by the external electronic device in response to the transmitted power using the wireless communication circuit; obtain power loss based on the obtained data; stop transmitting the power to the external electronic device when the power loss exceeds a first threshold; and stop transmitting the power to the external electronic device according to whether an event related the power loss occurs even when the power loss is lower than the first threshold.

公开(公告)号：US20210021273A1

公开(公告)日：2021-01-21

申请号：US16842281

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong JUNG ,  Sangdon JUNG ,  Seunghyun OH ,  Kyungmin LEE

IPC: H03L7/107 ,  H03L7/089 ,  H03L7/099

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.