公开(公告)号：US10861537B1

公开(公告)日：2020-12-08

申请号：US16668886

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Abhijith Prakash

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/408

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

公开(公告)号：US12148478B2

公开(公告)日：2024-11-19

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US11894072B2

公开(公告)日：2024-02-06

申请号：US17724769

申请日：2022-04-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/08 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.

公开(公告)号：US20230130394A1

公开(公告)日：2023-04-27

申请号：US17511818

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

公开(公告)号：US11501837B1

公开(公告)日：2022-11-15

申请号：US17318529

申请日：2021-05-12

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash

IPC: G11C11/00 ,  G11C16/30 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

Abstract: A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

公开(公告)号：US20220336019A1

公开(公告)日：2022-10-20

申请号：US17231490

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C11/56

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses and bitscan operations are skipped.

公开(公告)号：US11468950B1

公开(公告)日：2022-10-11

申请号：US17231490

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C11/56 ,  H01L27/11565 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses and bitscan operations are skipped.

公开(公告)号：US11456042B1

公开(公告)日：2022-09-27

申请号：US17229705

申请日：2021-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Jiahui Yuan ,  Abhijith Prakash

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

公开(公告)号：US20220293197A1

公开(公告)日：2022-09-15

申请号：US17195878

申请日：2021-03-09

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number.

公开(公告)号：US11410739B1

公开(公告)日：2022-08-09

申请号：US17206318

申请日：2021-03-19

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses.