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41.发明申请SYSTEMS AND METHODS FOR SUB-ZERO THRESHOLD CHARACTERIZATION IN A MEMORY CELL 审中-公开用于在存储器单元中进行零次阈值表征的系统和方法公开(公告)号：US20160379718A1
公开(公告)日：2016-12-29
申请号：US15195856
申请日：2016-06-28
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC classification number: G11C16/3427 , G11C16/3418 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/50004
Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于表征固态存储器的系统和方法。 在一个实施例中，系统和方法可以包括将固态存储器件的第一单元编程为负电压，将固态存储器件的第二单元编程为正电压，其中第二单元与第一单元相邻 计算编程到第一单元的负电压上的电压偏移，表征作为中间电压的第一单元上的移位电压电平，以及从中间电压减去电压偏移以产生第一单元上的实际电压。
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42.发明申请SYSTEMS AND METHODS FOR LATENCY BASED DATA RECYCLING IN A SOLID STATE MEMORY SYSTEM 审中-公开用于在固态存储器系统中基于数据的数据循环的系统和方法公开(公告)号：US20160357485A1
公开(公告)日：2016-12-08
申请号：US15245000
申请日：2016-08-23
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Ning Chen , Erich F. Haratsch , Zhengang Chen
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/7205 , G11C16/08 , G11C29/52 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1128 , H03M13/3746 , H03M13/6505
Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。 所述系统和方法包括接收保存在存储器件中的数据集，将数据解码算法的至少一次迭代应用于数据解码器电路的数据集，以产生解码输出，对数据解码算法的迭代次数进行计数 应用于数据集以产生迭代计数，并将数据集再循环到存储器件。 至少部分地基于迭代次数来触发回收。
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43.发明申请公开(公告)号：US20160308556A1
公开(公告)日：2016-10-20
申请号：US15195879
申请日：2016-06-28
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Erich F. Haratsch , Ning Chen
CPC classification number: H03M13/1111 , G06F11/10 , G11B20/1833 , H03M13/6325 , H03M13/6343 , H03M13/658
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于在数据解码电路中缩放消息的系统和方法。 在一个实施例中，系统和方法包括应用可变节点算法，应用校验节点算法，计算第一数量的误差，计算第二数量的误差，计算第一和第二数量的误差之间的差，乘以标量 值以产生缩放的消息集合，并且将变量节点算法重新应用于缩放的消息集合。
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Patent Agency Ranking
44.发明授权Systems and methods for latency based data recycling in a solid state memory system 有权在固态存储器系统中基于等待时间的数据回收的系统和方法公开(公告)号：US09424179B2
公开(公告)日：2016-08-23
申请号：US14072530
申请日：2013-11-05
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Ning Chen , Erich F. Haratsch , Zhengang Chen
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/7205 , G11C16/08 , G11C29/52 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1128 , H03M13/3746 , H03M13/6505
Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。 所述系统和方法包括接收保存在存储器件中的数据集，将数据解码算法的至少一次迭代应用于数据解码器电路的数据集，以产生解码输出，对数据解码算法的迭代次数进行计数 应用于数据集以产生迭代计数，并将数据集再循环到存储器件。 至少部分地基于迭代次数来触发回收。
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45.发明授权Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes 有权使用具有多个纠错码的存储控制器中的纠错能力的概率密度函数进行纠错码（ECC）选择公开(公告)号：US09419655B2
公开(公告)日：2016-08-16
申请号：US14264419
申请日：2014-04-29
Applicant: Seagate Technology LLC
Inventor： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC classification number: H03M13/1157 , G06F11/1004 , G06F11/1048 , G06F11/108 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/1174 , H03M13/35 , H03M13/353 , H03M13/356 , H03M13/3715 , H03M13/611 , H03M13/6513 , H03M13/6516
Abstract: An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.
Abstract translation: 一种装置包括纠错码电路和纠错码选择电路。 纠错码电路可以被配置为使用多个纠错码中的任何一个对数据进行编码和解码。 误差校正码选择电路可以被配置为响应于一个或多个可靠性统计和多个特征分布特性中的每个的多个误差校正码来使用纠错码电路中的哪个纠错码来对数据进行编码和解码 的纠错码。
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46.发明授权Systems and methods for sub-zero threshold characterization in a memory cell 有权在存储器单元中用于零零阈值表征的系统和方法公开(公告)号：US09378840B2
公开(公告)日：2016-06-28
申请号：US14085553
申请日：2013-11-20
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC classification number: G11C16/3427 , G11C16/3418 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/50004
Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于表征固态存储器的系统和方法。 在一个实施例中，系统和方法可以包括将固态存储器件的第一单元编程为负电压，将固态存储器件的第二单元编程为正电压，其中第二单元与第一单元相邻 计算编程到第一单元的负电压上的电压偏移，表征作为中间电压的第一单元上的移位电压电平，以及从中间电压减去电压偏移以产生第一单元上的实际电压。
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47.发明授权公开(公告)号：US09378765B2
公开(公告)日：2016-06-28
申请号：US14261333
申请日：2014-04-24
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yu Cai , Yunxiang Wu , Erich F. Haratsch , Ning Chen
CPC classification number: H03M13/1111 , G06F11/10 , G11B20/1833 , H03M13/6325 , H03M13/6343 , H03M13/658
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.
Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于在数据解码电路中缩放消息的系统和方法。 在一个实施例中，系统和方法包括应用可变节点算法，应用校验节点算法，计算第一数量的误差，计算第二数量的误差，计算第一和第二数量的误差之间的差，乘以标量 值以产生缩放的消息集合，并且将变量节点算法重新应用于缩放的消息集合。
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48.发明授权Systems and methods for soft data utilization in a solid state memory system 有权在固态存储器系统中软数据利用的系统和方法公开(公告)号：US09201729B2
公开(公告)日：2015-12-01
申请号：US14072574
申请日：2013-11-05
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Yunxiang Wu , Yu Cai , Erich F. Haratsch
CPC classification number: H03M13/1111 , G06F11/1008 , G06F11/1012 , G06F11/1068 , H03M13/45 , H03M13/611
Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。
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