公开(公告)号：US11462251B2

公开(公告)日：2022-10-04

申请号：US17195294

申请日：2021-03-08

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C7/10

摘要： A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks generated by dividing an internal clock.

公开(公告)号：US11443782B2

公开(公告)日：2022-09-13

申请号：US17306598

申请日：2021-05-03

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C7/22 ,  G11C7/10

摘要： An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

公开(公告)号：US11380383B2

公开(公告)日：2022-07-05

申请号：US17011496

申请日：2020-09-03

申请人： SK hynix Inc.

发明人： Kyung Mook Kim ,  Woongrae Kim ,  Geun Ho Choi

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

摘要： An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

公开(公告)号：US11373698B2

公开(公告)日：2022-06-28

申请号：US15987586

申请日：2018-05-23

申请人： SK hynix Inc.

发明人： Woongrae Kim ,  Tae-Yong Lee

IPC分类号： G11C16/10 ,  G11C11/406 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/02 ,  G11C11/4076 ,  G11C29/04

摘要： A semiconductor device includes a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.

公开(公告)号：US11308998B2

公开(公告)日：2022-04-19

申请号：US17158455

申请日：2021-01-26

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C7/00 ,  G11C7/10

摘要： An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.

公开(公告)号：US20210407574A1

公开(公告)日：2021-12-30

申请号：US17097151

申请日：2020-11-13

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C11/4076 ,  G11C11/408 ,  G11C11/4096

摘要： A semiconductor memory device includes: a memory cell array including banks; a command/address buffer receiving a command/address based on a system clock; a data input/output circuit inputting/outputting data based on a data clock; a mode control circuit generating mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data clock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system clock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system clock during a read operation.

公开(公告)号：US11176976B2

公开(公告)日：2021-11-16

申请号：US16989320

申请日：2020-08-10

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C7/22 ,  G06F11/10 ,  G11C7/10

摘要： A semiconductor memory device includes a read/write control circuit and an error correction circuit. The read/write control circuit generates an internal write signal after generating an internal read signal from one of a plurality of shifted signals which are generated by shifting a read-modify-write command according to a frequency of a clock signal. The error correction circuit corrects an error included in internal data by performing a logical operation of read data generated by the internal read signal and the internal data to generate write data. The internal read signal is enabled by a write set signal during the read-modify-write operation.

公开(公告)号：US11048441B2

公开(公告)日：2021-06-29

申请号：US16677557

申请日：2019-11-07

申请人： SK hynix Inc.

发明人： Woongrae Kim ,  Woo Jin Kang ,  Seung Wook Oh

IPC分类号： G11C7/22 ,  G06F3/06 ,  G11C8/18

摘要： A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

公开(公告)号：US11037609B2

公开(公告)日：2021-06-15

申请号：US17081516

申请日：2020-10-27

申请人： SK hynix Inc.

发明人： Woongrae Kim ,  Tae Yong Lee

IPC分类号： G11C7/12 ,  G11C8/12 ,  G11C7/10 ,  G11C8/10 ,  G11C11/419 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/418 ,  G11C11/408

摘要： A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.

公开(公告)号：US10950283B1

公开(公告)日：2021-03-16

申请号：US16787202

申请日：2020-02-11

申请人： SK hynix Inc.

发明人： Woongrae Kim

IPC分类号： G11C16/16 ,  G11C7/22 ,  G11C8/18

摘要： A semiconductor device includes a latch signal generation circuit and a training result signal generation circuit. The latch signal generation circuit latches a first internal control signal and a second internal control signal to generate a first latch signal and a second latch signal. The first internal control signal is generated based on a first internal clock signal and a control signal, and the second internal control signal is generated. The training result signal generation circuit is synchronized with a first alignment pulse and a second alignment pulse generated based on the first latch signal and the latch signal, thereby generating a training result signal from the first and second latch signals.