公开(公告)号：US11048441B2

公开(公告)日：2021-06-29

申请号：US16677557

申请日：2019-11-07

Applicant: SK hynix Inc.

Inventor： Woongrae Kim ,  Woo Jin Kang ,  Seung Wook Oh

IPC: G11C7/22 ,  G06F3/06 ,  G11C8/18

Abstract: A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

公开(公告)号：US10284156B2

公开(公告)日：2019-05-07

申请号：US15668097

申请日：2017-08-03

Applicant: SK hynix Inc.

Inventor： Dong Hyun Kim ,  Eun Ji Choi ,  Yo Han Jeong ,  Soon Ku Kang ,  Woo Jin Kang ,  Kwan Su Shon ,  Hyun Bae Lee ,  Tae Jin Hwang

IPC: H03F3/45 ,  G05F1/565 ,  H03M1/00

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.