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113 条记录 (耗时 0.026 秒)

    Apparatus and method for controlling supply of power for refresh operation
    1.
    发明授权
    Apparatus and method for controlling supply of power for refresh operation 有权

    公开(公告)号：US12062390B2

    公开(公告)日：2024-08-13

    申请号：US17824303

    申请日：2022-05-25

    申请人： SK hynix Inc.

    发明人： Woongrae Kim

    IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/408

    CPC分类号： G11C11/40615 ,  G11C11/4085 ,  G11C11/4087

    摘要： A memory device includes: a refresh control circuit configured to generate a self-refresh command and a refresh address, word line control circuits configured to control a refresh operation of a plurality of word lines, a group management circuit configured to classify N address groups by grouping the refresh addresses to be generated by the refresh control circuit and to select from the N address groups, a current address group including a refresh address to be currently generated and a subsequent address group including a refresh address to be generated after the current address group according to the predetermined order, a row control circuit configured to group the plurality of word line control circuits with N control signals respectively corresponding to the N address groups, respectively, and a supply control circuit configured to activate signals corresponding to the current and subsequent address groups among the N control signals.

    Semiconductor memory device and refresh operation method, including input circuit, plurality of latches, plurality of counters and refresh controller for generating reset signals
    3.
    发明授权
    Semiconductor memory device and refresh operation method, including input circuit, plurality of latches, plurality of counters and refresh controller for generating reset signals 有权

    公开(公告)号：US11551740B2

    公开(公告)日：2023-01-10

    申请号：US17353004

    申请日：2021-06-21

    申请人： SK hynix Inc.

    发明人： Woongrae Kim ,  Kwi Dong Kim

    IPC分类号： G11C11/406

    摘要： A semiconductor memory device includes: an input control circuit suitable for providing an active address which is input together with an active command, as an input address; a plurality of latches suitable for sequentially storing, as a latch address, the input address according to input control signals and outputting the latch addresses as a target address according to output control signals; a plurality of counters respectively corresponding to the latches and each suitable for increasing, when the active address matches the latch address stored in the latch, a counting value corresponding to the latch; and a refresh controller suitable for dividing the counters and the latches into a plurality of groups based on the counting values and generating, in response to a refresh command, reset signals for initializing the counters included in one group of the groups.

    Electronic devices mitigating degradation of MOS transistors
    4.
    发明授权
    Electronic devices mitigating degradation of MOS transistors 有权

    公开(公告)号：US11514978B2

    公开(公告)日：2022-11-29

    申请号：US17158789

    申请日：2021-01-26

    申请人： SK hynix Inc.

    发明人： Woongrae Kim

    IPC分类号： G11C11/4096 ,  G11C11/4078 ,  G11C11/4074 ,  G11C11/406

    摘要： An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.

    System for performing reference voltage training operation
    5.
    发明授权
    System for performing reference voltage training operation 有权

    公开(公告)号：US11508418B2

    公开(公告)日：2022-11-22

    申请号：US16989392

    申请日：2020-08-10

    申请人： SK hynix Inc.

    发明人： Woongrae Kim

    IPC分类号： G11C5/14 ,  G11C7/10

    摘要： A system to perform a reference voltage training operation may include: a controller configured to output a dock signal, a chip selection signal, a command address and data; and a semiconductor device configured to enter a training mode to control the level of a reference voltage when the chip selection signal and the command address are a first logic level combination in synchronization with the clock signal, configured to enter an ID setting mode to set a storage ID when the chip selection signal and the command address are a second logic level combination, and configured to enter an ID selection mode to update a voltage code that is generated in the training mode when the chip selection signal and the command address are a third logic level combination.

    Semiconductor devices
    6.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11495286B2

    公开(公告)日：2022-11-08

    申请号：US17353267

    申请日：2021-06-21

    申请人： SK hynix Inc.

    发明人： Woongrae Kim

    IPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4093

    摘要： A semiconductor device includes a read write control circuit configured to generate first and second write command pulses from an external control signal for performing a write operation; a flag generation circuit configured to generate a write flag, a write shifting flag, an internal write flag and an internal write shifting flag based on the second write command pulse, a bank mode signal and a bank group mode signal; and a bank group selection signal generation circuit configured to store a bank address based on an write input control pulse generated from the second write command pulse in a bank mode, and output the stored bank address as a bank group selection signal based on a write output control pulse generated from the write flag.

    Integrated circuit
    9.
    发明授权
    Integrated circuit 有权

    公开(公告)号：US11329651B2

    公开(公告)日：2022-05-10

    申请号：US17150680

    申请日：2021-01-15

    申请人： SK hynix Inc.

    发明人： Woongrae Kim

    IPC分类号： H03K21/10

    摘要： An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.

    Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus
    10.
    发明授权
    Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus 有权

    公开(公告)号：US11264076B2

    公开(公告)日：2022-03-01

    申请号：US16661342

    申请日：2019-10-23

    申请人： SK hynix Inc.

    发明人： Woongrae Kim ,  Byeong Cheol Lee ,  Se Won Lee

    IPC分类号： G11C11/406 ,  G11C11/4074 ,  G11C8/10

    摘要： A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.