公开(公告)号：US10796737B1

公开(公告)日：2020-10-06

申请号：US16725174

申请日：2019-12-23

申请人： SK hynix Inc.

发明人： Seung Wook Oh ,  Young Suk Seo ,  Da In Im

IPC分类号： G11C7/10 ,  H03K5/135 ,  G11C7/22 ,  G11C8/10

摘要： A semiconductor apparatus includes a clock path, a command path, a delay monitoring circuit, and an output control circuit. The clock path generates a delay clock signal by delaying a clock signal. The command path generates an output command signal from on one of a command signal and the clock signal, based on a monitoring signal. The delay monitoring circuit generates a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled. The output control circuit generates an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.

公开(公告)号：US11133055B1

公开(公告)日：2021-09-28

申请号：US17009413

申请日：2020-09-01

申请人： SK hynix Inc.

发明人： Woongrae Kim ,  Seung Wook Oh

IPC分类号： G11C7/22 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4076

摘要： An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

公开(公告)号：US11615822B2

公开(公告)日：2023-03-28

申请号：US17499384

申请日：2021-10-12

申请人： SK hynix Inc.

发明人： Min Su Park ,  Seung Wook Oh ,  Jin Il Chung

IPC分类号： G11C7/10

摘要： An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

公开(公告)号：US11372591B2

公开(公告)日：2022-06-28

申请号：US17157516

申请日：2021-01-25

申请人： SK hynix Inc.

发明人： Seung Wook Oh ,  Chang Hyun Kim ,  Young Jae An ,  Woong Rae Kim

IPC分类号： G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G11C7/20 ,  G11C8/10

摘要： A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

公开(公告)号：US10924114B2

公开(公告)日：2021-02-16

申请号：US16659852

申请日：2019-10-22

申请人： SK hynix Inc.

发明人： Young Suk Seo ,  Seung Wook Oh ,  Da In Im

IPC分类号： G06F1/10 ,  H03K19/003

摘要： A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

公开(公告)号：US11048441B2

公开(公告)日：2021-06-29

申请号：US16677557

申请日：2019-11-07

申请人： SK hynix Inc.

发明人： Woongrae Kim ,  Woo Jin Kang ,  Seung Wook Oh

IPC分类号： G11C7/22 ,  G06F3/06 ,  G11C8/18

摘要： A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

公开(公告)号：US10891995B2

公开(公告)日：2021-01-12

申请号：US16518635

申请日：2019-07-22

申请人： SK hynix Inc.

发明人： Geun Ho Choi ,  Seung Wook Oh ,  Jin Il Chung

IPC分类号： G11C7/22 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/16

摘要： A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

公开(公告)号：US10886927B2

公开(公告)日：2021-01-05

申请号：US16736688

申请日：2020-01-07

申请人： SK hynix Inc.

发明人： Seung Wook Oh ,  Jin Il Chung

IPC分类号： G06F1/10 ,  H03L7/081 ,  G06F1/06 ,  G06F1/12 ,  H03K19/20

摘要： A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

公开(公告)号：US11233511B2

公开(公告)日：2022-01-25

申请号：US17142103

申请日：2021-01-05

申请人： SK hynix Inc.

发明人： Young Suk Seo ,  Seung Wook Oh ,  Da In Im

IPC分类号： G06F1/10 ,  H03K19/003

摘要： A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

公开(公告)号：US11206022B2

公开(公告)日：2021-12-21

申请号：US17142103

申请日：2021-01-05

申请人： SK hynix Inc.

发明人： Young Suk Seo ,  Seung Wook Oh ,  Da In Im

IPC分类号： G06F1/10 ,  H03K19/003

摘要： A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.