公开(公告)号：US11803226B2

公开(公告)日：2023-10-31

申请号：US16874020

申请日：2020-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Pasquale Butta′ ,  Sergio Abenda

IPC: G06F1/3234 ,  H03K3/037 ,  G06F1/3296

CPC classification number: G06F1/325 ,  G06F1/3243 ,  H03K3/037

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

公开(公告)号：US11703897B2

公开(公告)日：2023-07-18

申请号：US16810639

申请日：2020-03-05

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Michel Cuenca ,  Bruno Gailhard ,  Daniele Mangano

IPC: G05F1/56

CPC classification number: G05F1/56

Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

公开(公告)号：US20230087239A1

公开(公告)日：2023-03-23

申请号：US18059812

申请日：2022-11-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Benoit Marchand ,  Hamilton Emmanuel Querino De Carvalho ,  Achraf Dhayni ,  Daniele Mangano

IPC: H03B5/36 ,  G06F1/10 ,  H03F3/24 ,  H04B1/04

Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

公开(公告)号：US11496170B2

公开(公告)日：2022-11-08

申请号：US17180751

申请日：2021-02-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

Inventor： Benoit Marchand ,  Hamilton Emmanuel Querino De Carvalho ,  Daniele Mangano ,  Santo Leotta

IPC: H04B1/12 ,  H04B1/40 ,  H04B1/16

Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.

公开(公告)号：US10788870B2

公开(公告)日：2020-09-29

申请号：US16405086

申请日：2019-05-07

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Gaetano Di Stefano ,  Mirko Dondini

IPC: G06F1/24 ,  G06F11/267 ,  H03K3/037

Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.

公开(公告)号：US10451703B2

公开(公告)日：2019-10-22

申请号：US16213534

申请日：2018-12-07

Applicant: STMicroelectronics S.r.l.

Inventor： Riccardo Condorelli ,  Daniele Mangano

IPC: G01R35/00 ,  G01R27/26 ,  G01R27/02 ,  G01D3/028 ,  G01D5/24 ,  H02J7/04 ,  H02J7/34

Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

公开(公告)号：US10162038B2

公开(公告)日：2018-12-25

申请号：US14739195

申请日：2015-06-15

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Riccardo Condorelli ,  Daniele Mangano

IPC: G01R35/00 ,  G01R27/26 ,  G01D5/24 ,  H02J7/04 ,  G01D3/028 ,  H02J7/34 ,  G01R27/02

Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

公开(公告)号：US10120006B2

公开(公告)日：2018-11-06

申请号：US15070509

申请日：2016-03-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Riccardo Condorelli ,  Daniele Mangano

IPC: G01R27/26 ,  G01D5/20 ,  H03K17/95

Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.

公开(公告)号：US10019399B2

公开(公告)日：2018-07-10

申请号：US14940026

申请日：2015-11-12

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F17/50 ,  G06F13/36 ,  H04L12/933 ,  G06F15/78 ,  H04L12/935 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4068 ,  G06F15/7807 ,  G06F15/7825 ,  G06F17/5077 ,  G06F2217/04 ,  G06F2217/06 ,  H04L49/109 ,  H04L49/15 ,  H04L49/3009

Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.

公开(公告)号：US20170270070A1

公开(公告)日：2017-09-21

申请号：US15608857

申请日：2017-05-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F13/40 ,  G06F13/14 ,  G06F15/78

CPC classification number: G06F13/4027 ,  G06F13/14 ,  G06F15/7825 ,  G06F2213/0038 ,  H04Q2213/13399 ,  H04Q2213/399

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.