公开(公告)号：US20160182225A1

公开(公告)日：2016-06-23

申请号：US15056844

申请日：2016-02-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: H04L9/08 ,  G06F12/14 ,  G06F3/06

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

Abstract translation: 公开了一种用于处理存储在部件上的内容的方法。 利用第一加密密钥对第一存储器的第一分区进行加密，并且用第二加密密钥对第一存储器的第二分区进行加密。 第二加密密钥与第一加密密钥不同。 第一加密密钥存储在组件的存储寄存器中，第二加密密钥存储在非易失性存储器的第一位置。 第一位置的存储器地址存储在第一存储器的第一分区中。

公开(公告)号：US09223368B2

公开(公告)日：2015-12-29

申请号：US14446814

申请日：2014-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Fabrice Marinet

IPC: G06F17/50 ,  G06F1/26 ,  G06F21/72 ,  G06K19/073 ,  H04L9/00 ,  H01L21/762 ,  H03K3/84 ,  H03K19/003 ,  H01L23/00

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract translation: 本公开涉及一种电子微电路中的对策方法，包括由微电路的电路执行的连续处理阶段，以及根据为该电路产生的随机值调整电路与电路的接地端之间的电源电压 处理阶段，在电路执行的每个处理阶段。

公开(公告)号：US09082609B2

公开(公告)日：2015-07-14

申请号：US13953003

申请日：2013-07-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Pascal Fornara

IPC: H01L29/94 ,  H01L27/00 ,  G11C27/02 ,  H01L49/02 ,  G04F10/10

CPC classification number: H01L27/00 ,  G04F10/10 ,  G11C27/024 ,  H01L28/40 ,  H01L28/60

Abstract: An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.

Abstract translation: 一种电荷流动元件，包括在绝缘支撑件上，具有至少一部分能够通过隧道效应使电荷流动的介电层的第一电极的堆叠和第二电极，其中至少一个所述电极 由未掺杂的多晶硅制成。

公开(公告)号：US20150019885A1

公开(公告)日：2015-01-15

申请号：US14446814

申请日：2014-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Fabrice Marinet

IPC: G06F1/26 ,  H03K3/84 ,  H03K19/003 ,  H01L21/762

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract translation: 本公开涉及一种电子微电路中的对策方法，包括由微电路的电路执行的连续处理阶段，以及根据为该电路产生的随机值调整电路与电路的接地端之间的电源电压 处理阶段，在电路执行的每个处理阶段。

公开(公告)号：US11379238B2

公开(公告)日：2022-07-05

申请号：US16833012

申请日：2020-03-27

Applicant: PROTON WORLD INTERNATIONAL N.V. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Michael Peeters ,  Fabrice Marinet

IPC: G06F9/30

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

公开(公告)号：US20200233815A1

公开(公告)日：2020-07-23

申请号：US16841403

申请日：2020-04-06

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Michael Peeters ,  Fabrice Marinet ,  Jean-Louis Modave

IPC: G06F12/14 ,  G06F21/79 ,  G06F12/02 ,  G06F21/72

Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.

公开(公告)号：US10361164B2

公开(公告)日：2019-07-23

申请号：US15446472

申请日：2017-03-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Thomas Ordas ,  Alexandre Sarafianos ,  Fabrice Marinet ,  Stephane Chesnais

IPC: H01L23/00 ,  H01L23/62 ,  H01L27/02 ,  H01L23/522 ,  G06F21/75 ,  G06F21/87 ,  G06K19/073 ,  H01L23/528

Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults.

公开(公告)号：US10169622B2

公开(公告)日：2019-01-01

申请号：US15836626

申请日：2017-12-08

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Louis Modave ,  Fabrice Marinet ,  Denis Farison

IPC: G06F21/85 ,  G06F21/73 ,  G06F21/81 ,  G11C27/00

Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.

公开(公告)号：US10148421B2

公开(公告)日：2018-12-04

申请号：US15221749

申请日：2016-07-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Thomas Ordas ,  Alexandre Sarafianos ,  Stephane Chesnais ,  Fabrice Marinet

IPC: G06F21/00 ,  H04L9/00 ,  G06K19/073 ,  G09C1/00 ,  H04K3/00 ,  G06F1/04 ,  G06F21/72 ,  H01L23/528 ,  H03K3/84 ,  H03K5/01 ,  H03K5/00

Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

公开(公告)号：US20180137061A1

公开(公告)日：2018-05-17

申请号：US15486947

申请日：2017-04-13

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Michael Peeters ,  Fabrice Marinet ,  Jean-Louis Modave

IPC: G06F12/14 ,  G06F21/72

CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F21/72 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/402 ,  H04L2209/12

Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.