Abstract:
A copper plasma etching method according an exemplary embodiment includes: placing a substrate on a susceptor in a process chamber of a plasma etching apparatus; supplying an etching gas that include hydrogen chloride into the process chamber; plasma-etching a conductor layer that include copper in the substrate; and maintaining a temperature of the susceptor at 10° C. or less during the plasma-etching.
Abstract:
A method of manufacturing a thin film transistor array substrate includes providing a plurality of gate lines and a plurality of data lines on a first substrate, providing an organic layer on the gate lines and the data lines, providing a first electrode on the organic layer, providing a passivation layer on the first electrode, providing a second electrode on the passivation layer, providing a first cover layer on the second electrode to cover the second electrode, providing a plurality of photosensitive layer patterns on the first cover layer, providing a plurality of first cutout patterns in the first cover layer and a plurality of second cutout patterns in the second electrode using the photosensitive layer patterns as an etch mask, and providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask.
Abstract:
A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.
Abstract:
A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.
Abstract:
A liquid crystal display is provided. The liquid crystal display includes a substrate, a thin film transistor disposed on the substrate, a pixel electrode connected with a terminal of the thin film transistor, a microcavity disposed on the pixel electrode, the microcavity including a liquid crystal injection hole disposed at an edge of the microcavity, a supporting member disposed on the microcavity, a first hydrophobic layer disposed on an edge portion of the supporting member, and a capping layer disposed on the supporting member with the capping layer covering the liquid crystal injection hole.