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    Semiconductor memory device
    42.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11956957B2

    公开(公告)日：2024-04-09

    申请号：US17203122

    申请日：2021-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Young Kim ,  Woo Sung Yang ,  Sung-Min Hwang ,  Suk Kang Sung ,  Joon-Sung Lim

    IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

    Semiconductor memory device and electronic system including the same
    43.
    发明授权
    Semiconductor memory device and electronic system including the same 有权

    公开(公告)号：US11844211B2

    公开(公告)日：2023-12-12

    申请号：US17340148

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

    IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

    Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

    Semiconductor memory device, electronic system including the same, and method for fabricating the same
    47.
    发明授权
    Semiconductor memory device, electronic system including the same, and method for fabricating the same 有权

    公开(公告)号：US11574883B2

    公开(公告)日：2023-02-07

    申请号：US17389841

    申请日：2021-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

    IPC: H01L25/065 ,  H01L23/535 ,  H01L23/00 ,  H01L25/18 ,  H01L21/768 ,  H01L25/00

    Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

    Three-dimensional semiconductor memory device
    48.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11456254B2

    公开(公告)日：2022-09-27

    申请号：US17027734

    申请日：2020-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jisoo Chung ,  Kang-Won Lee ,  Sung-Min Hwang

    IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

    Abstract: A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and the second block.

    Three-dimensional semiconductor memory device and method of fabricating the same
    50.
    发明授权
    Three-dimensional semiconductor memory device and method of fabricating the same 有权

    公开(公告)号：US10818678B2

    公开(公告)日：2020-10-27

    申请号：US15954151

    申请日：2018-04-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Min Hwang ,  Dong-Sik Lee ,  Joon-Sung Lim

    IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11575

    Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

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