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    EXTREME ULTRAVIOLET LIGHT SOURCE SYSTEMS
    41.
    发明申请
    EXTREME ULTRAVIOLET LIGHT SOURCE SYSTEMS 有权

    公开(公告)号：US20220104336A1

    公开(公告)日：2022-03-31

    申请号：US17325327

    申请日：2021-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SUNGHYUP KIM ,  Myeongjun Gil ,  Yebin Nam ,  Sanghoon Lee ,  Injae Lee

    IPC: H05G2/00 ,  G03F7/20

    Abstract: Extreme ultraviolet light source systems may include a chamber including a condensing mirror and having an intermediate focus, by which extreme ultraviolet light reflected from the condensing mirror is emitted along a first optical path, a blocking plate that may be on the chamber so as to intersect the first optical path and may include an opening through which the extreme ultraviolet light is emitted, a transparent cover on the blocking plate so as to cover the opening, a nozzle that may be between the chamber and the blocking plate so that an end portion faces the intermediate focus and may spray a first gas in a direction intersecting the first optical path, and an exhaust pipe between the chamber and the blocking plate so as to face the end portion of the nozzle.

    SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    42.
    发明申请
    SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220085047A1

    公开(公告)日：2022-03-17

    申请号：US17224695

    申请日：2021-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanghoon Lee

    IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

    Abstract: A semiconductor device includes a substrate having a first area and a second area and an active area limited by an isolation layer in the first area and the second area, a p-type gate electrode doped with p-type impurities and including a p-type lower gate layer and a p-type upper gate layer on the p-type lower gate layer with a first gate dielectric layer disposed between the active area and the p-type gate electrode in the first area, and an n-type gate electrode doped with n-type impurities and including an n-type lower gate layer and an n-type upper gate layer on the n-type lower gate layer with a second gate dielectric layer disposed between the active area and the n-type gate electrode in the second area.

    DISPLAY APPARATUS AND DISPLAY CONTROL METHOD
    43.
    发明申请
    DISPLAY APPARATUS AND DISPLAY CONTROL METHOD 有权

    公开(公告)号：US20210149195A1

    公开(公告)日：2021-05-20

    申请号：US17095872

    申请日：2020-11-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daesu CHOI ,  Jigwang Kim ,  Jiwon Kim ,  Jaemin Soh ,  Kyehoon Lee ,  Sanghoon Lee

    IPC: G02B27/01 ,  G02B17/00 ,  G02B5/10

    Abstract: A display apparatus and a display control method are provided. The display apparatus includes: an image source configured to output a first image; a relay optics component configured to change a size of the first image and to transfer the first image; a surrounding structure provided around the image source or the relay optics component, and including a second image of a surrounding object; and a combiner configured to form a first virtual image by reflecting the first image, and to form a second virtual image around the first virtual image by reflecting the second image.

    SEMICONDUCTOR DEVICES
    44.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200381555A1

    公开(公告)日：2020-12-03

    申请号：US16815744

    申请日：2020-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon Lee ,  Krishna Bhuwalka ,  Myunggil Kang ,  Kyoungmin Choi

    IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423

    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

    I/Q mismatch compensation method and apparatus
    49.
    发明授权
    I/Q mismatch compensation method and apparatus 有权
    I / Q失配补偿方法和装置

    公开(公告)号：US09231715B2

    公开(公告)日：2016-01-05

    申请号：US14589584

    申请日：2015-01-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donghan Kim ,  Sungtae Choi ,  Jaehwa Kim ,  Yiju Roh ,  Sanghoon Lee

    IPC: H04B1/38 ,  H04B17/14 ,  H03D3/00 ,  H04L27/36 ,  H04L27/38 ,  H04B17/21 ,  H04B17/24 ,  H04L1/24

    CPC classification number: H04B17/14 ,  H03D3/009 ,  H04B17/21 ,  H04B17/24 ,  H04L1/243 ,  H04L27/364 ,  H04L27/3863

    Abstract: An In-phase/Quadrature phase (I/Q) mismatch compensation method of a transceiver is provided. The method includes establishing a first loopback path between a transmitter and a receiver, transmitting a training sequence from the transmitter to the receiver through the established first loopback path, acquiring, at the receiver, a first correlation result value by correlating the training sequence received through the established first loopback path, establishing a second loopback path between the transmitter and the receiver, transmitting the training sequence from the transmitter to the receiver through the established second loopback path, acquiring, at the receiver, a second correlation result value by correlating the training sequence received through the second loopback path, and estimating I/Q mismatch values of the transmitter and the receiver using the first and second correlation result values.

    Abstract translation: 提供收发器的同相/正交相位（I / Q）失配补偿方法。 该方法包括建立发射机和接收机之间的第一环回路径，通过建立的第一环回路径将训练序列从发射机发射到接收机，在接收机处通过将接收到的训练序列相关联来获取第一相关结果值 建立的第一环回路径，在发射机和接收机之间建立第二环回路径，通过所建立的第二环回路径将训练序列从发射机发送到接收机，在接收机处通过将训练相关联来获取第二相关结果值 通过第二环回路径接收的序列，以及使用第一和第二相关结果值估计发射机和接收机的I / Q不匹配值。

    Electronic apparatus and control method thereof
    50.
    发明授权
    Electronic apparatus and control method thereof 有权

    公开(公告)号：US12224660B2

    公开(公告)日：2025-02-11

    申请号：US18094769

    申请日：2023-01-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Duhee Jang ,  Wonmyung Woo ,  Jeongil Kang ,  Sanghoon Lee

    IPC: H02M1/42 ,  G05F1/70 ,  H02M7/06

    Abstract: The electronic apparatus including a power factor correction (PFC) circuit and a control circuit configured to control an operation of the PFC circuit is provided. The PFC circuit includes a first inductor part connected to one end of an AC voltage part and a first switch connected to a first inductor in series; a second inductor part connected to another end of the AC voltage part and a second switch connected to a second inductor in series; an output part connected to the first inductor part and the second inductor part; and a switching part, and the control circuit identically applies a switch on/off signal to the first switch and the second switch, and selectively applies a switch on/off signal to the third switch or the fourth switch based on a magnitude of an input voltage input through the AC voltage part.

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