SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20250015134A1

    公开(公告)日:2025-01-09

    申请号:US18676686

    申请日:2024-05-29

    Abstract: A semiconductor device includes an active region that extends on the substrate in a first direction; a plurality of semiconductor layers disposed on the active region and that are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure disposed on the substrate and that crosses the active region and the plurality of semiconductor layers, surrounds each of the plurality of semiconductor layers, and extends in a second direction; a source/drain region disposed on at least one side of the gate structure and in contact with a portion of the plurality of semiconductor layers; and an epitaxial layer that is spaced apart from an uppermost semiconductor layer, is disposed below the source/drain region and between the active region and the source/drain region, and is in contact with at least a portion of the side surfaces of the lowermost semiconductor layer.

    SEMICONDUCTOR DEVICES
    2.
    发明申请

    公开(公告)号:US20220406919A1

    公开(公告)日:2022-12-22

    申请号:US17575856

    申请日:2022-01-14

    Abstract: A semiconductor device includes: an active region extending on a substrate in a first direction; a plurality of semiconductor layers spaced apart from each other vertically on the active region, including a lower semiconductor layer and an uppermost semiconductor layer disposed above the lower semiconductor layer and having a thickness greater than that of the lower semiconductor layer; a gate structure extending on the substrate in a second direction, perpendicular to the first direction, and including a gate electrode at least partially surrounding each of the plurality of semiconductor layers; a spacer structure disposed on both sidewalls of the gate structure; and source/drain regions disposed on the active region on both sides of the gate structure and contacting the plurality of semiconductor layers.

    Resistance measuring structures of stacked devices

    公开(公告)号:US12274092B2

    公开(公告)日:2025-04-08

    申请号:US18406345

    申请日:2024-01-08

    Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

    公开(公告)号:US20230131215A1

    公开(公告)日:2023-04-27

    申请号:US17863741

    申请日:2022-07-13

    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor structure extending from a substrate in a first direction and having first and second regions; forming a sacrificial gate pattern intersecting the first region of the semiconductor structure and extending in a second direction perpendicular to the first direction; reducing a width in the second direction of the second region of the semiconductor structure exposed to at least one side of the sacrificial gate pattern; forming at least one recess portion by removing a portion of the second region of the semiconductor structure; forming one or more source/drain regions in the recess portion of the semiconductor structure on at least one side of the sacrificial gate pattern; forming at least one gap region by removing the sacrificial gate pattern; and forming a gate structure by depositing a gate dielectric layer and a gate electrode in the gap region.

    SEMICONDUCTOR DEVICES
    5.
    发明申请

    公开(公告)号:US20220115539A1

    公开(公告)日:2022-04-14

    申请号:US17560804

    申请日:2021-12-23

    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

    Resistor with doped regions
    6.
    发明授权

    公开(公告)号:US11217578B2

    公开(公告)日:2022-01-04

    申请号:US16911795

    申请日:2020-06-25

    Abstract: A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

    INTEGRATED CIRCUIT DEVICE
    7.
    发明公开

    公开(公告)号:US20240321961A1

    公开(公告)日:2024-09-26

    申请号:US18613338

    申请日:2024-03-22

    Abstract: An integrated circuit device includes, a first nano-sheet stack including a plurality of nano-sheets arranged on a fin-type active region extending in a first horizontal direction, a gate line extending in a second horizontal direction on the fin-type active region, a vertical structure contacting the plurality of nano-sheets, and a first gate dielectric layer disposed between the gate line and the plurality of nano-sheets and between the gate line and the vertical structure, wherein the gate line includes a first sub-gate portion disposed under each of the plurality of nano-sheets, the first gate dielectric layer includes a first portion disposed between the gate line and the plurality of nano-sheets, and a second portion disposed between the first sub-gate portion and the vertical structure, and a thickness of the second portion in the second horizontal direction is greater than a thickness of the first portion in the vertical direction.

    Semiconductor devices
    10.
    发明授权

    公开(公告)号:US11705521B2

    公开(公告)日:2023-07-18

    申请号:US17560804

    申请日:2021-12-23

    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

Patent Agency Ranking