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    Nanowire field effect transistors
    44.
    发明授权
    Nanowire field effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US08648330B2

    公开(公告)日：2014-02-11

    申请号：US13343799

    申请日：2012-01-05

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/335 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近 覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料 在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区 渠道区域。

    Nanowire field effect transistors
    45.
    发明授权
    Nanowire field effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US08558219B2

    公开(公告)日：2013-10-15

    申请号：US13606365

    申请日：2012-09-07

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L21/335 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近 覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料 在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区 渠道区域。

    TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH
    46.
    发明申请
    TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH 失效
    两步氢化退火工艺，用于在均质玻璃板上形成均匀的非平面半导体器件

    公开(公告)号：US20130237038A1

    公开(公告)日：2013-09-12

    申请号：US13414744

    申请日：2012-03-08

    申请人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip

    发明人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip

    IPC分类号： H01L21/20 ,  B82Y40/00

    CPC分类号： H01L21/02104 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.

    摘要翻译： 已经开发了用于制造用于非平面半导体器件的半导体纳米线的两步骤氢退火工艺。 在悬浮半导体纳米线之前发生的两步氢退火工艺的第一部分中，至少半导体纳米线的侧壁的初始粗糙度减小，同时至少将纳米线的最底表面固定到 基板的最上表面。 在执行第一氢退火之后，将半导体纳米线悬浮，然后执行第二氢退火，这进一步降低了半导体纳米线的所有暴露表面的粗糙度并重新形成了半导体纳米线。 通过将退火分解为两个步骤，较窄的半导体纳米线在工艺和产量方面存在。

    Nanowire FET and FINFET Hybrid Technology
    47.
    发明申请
    Nanowire FET and FINFET Hybrid Technology 失效
    纳米线FET和FINFET混合技术

    公开(公告)号：US20130105897A1

    公开(公告)日：2013-05-02

    申请号：US13286311

    申请日：2011-11-01

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L27/1211 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/78696

    摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

    摘要翻译： 提供了混合纳米线FET和FinFET器件及其制造方法。 一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。 提供了在BOX上具有活性层的晶片。 有源层的第一区域变薄。 有机平面化层沉积在有源层上。 使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 使用第二硬掩模在活性层的第二区域中蚀刻金箔。 形成围绕每个纳米线的至少一部分的第一栅极堆叠。 形成第二栅极堆叠，覆盖每个散热片的至少一部分。 在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

    Nanowire Circuits in Matched Devices
    48.
    发明申请
    Nanowire Circuits in Matched Devices 有权
    匹配器件中的纳米线电路

    公开(公告)号：US20120280206A1

    公开(公告)日：2012-11-08

    申请号：US13554057

    申请日：2012-07-20

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L27/085 ,  H01L21/8232

    CPC分类号： H03K19/20 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/12 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696

    摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.

    摘要翻译： 存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET， 连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

    Nanowire FET with trapezoid gate structure
    49.
    发明授权
    Nanowire FET with trapezoid gate structure 有权
    具有梯形栅极结构的纳米线FET

    公开(公告)号：US08298881B2

    公开(公告)日：2012-10-30

    申请号：US12824293

    申请日：2010-06-28

    申请人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    发明人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/4232 ,  H01L29/513 ,  H01L29/66439

    摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

    摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。