公开(公告)号：US07514309B2

公开(公告)日：2009-04-07

申请号：US11184337

申请日：2005-07-19

申请人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Pacheco Rotondaro

发明人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。

公开(公告)号：US20080153221A1

公开(公告)日：2008-06-26

申请号：US11613798

申请日：2006-12-20

申请人： Seetharaman Sridhar ,  Majid Mansoori

发明人： Seetharaman Sridhar ,  Majid Mansoori

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

摘要： A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the method 300 may include forming a patterned photoresist layer 200 over a protection layer 190 in a NMOS region 50 and then etching exposed portions of the protection layer 190 in the PMOS region 60 to form extension sidewalls 210 on the transistors 30 in the PMOS region 60 plus a protective hardmask 220 over the NMOS region 50. The method 300 may further include forming the extension regions 70 for the PMOS region transistors 30, performing a recess etch 240 of active regions 230 of the PMOS region transistors 30, and forming the recessed strained epi regions 150.

摘要翻译： 用于通过单个掩模步骤306形成晶体管漏极延伸部分70和凹陷的应变外延区域150的方法300。 在示例性实施例中，方法300可以包括在NMOS区域50中的保护层190上形成图案化的光致抗蚀剂层200，然后蚀刻PMOS区域60中的保护层190的暴露部分，以在晶体管30上形成延伸侧壁210 在PMOS区域60中加上NMOS区域50上的保护硬掩模220。 方法300还可以包括形成用于PMOS区晶体管30的延伸区70，执行PMOS区晶体管30的有源区230的凹陷蚀刻240，并形成凹陷的应变外延区150。

公开(公告)号：US20080003772A1

公开(公告)日：2008-01-03

申请号：US11848187

申请日：2007-08-30

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20060073650A1

公开(公告)日：2006-04-06

申请号：US10949447

申请日：2004-09-24

申请人： Seetharaman Sridhar ,  Antonio Pacheco Rotondaro

发明人： Seetharaman Sridhar ,  Antonio Pacheco Rotondaro

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7843

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a portion of the cap poly layer from the PMOS region. Subsequently, the same resist mask and/or remaining portion of the cap poly layer is employed to form source/drain regions within the PMOS region by implanting a p-type dopant. Afterward, a cap poly thermal process is performed that causes tensile strain to be induced only in channel regions of devices located within the NMOS region. As a result, channel mobility and/or performance of devices located in the PMOS region is not substantially degraded.

摘要翻译： 本发明通过提供制造方法来促进半导体制造，该方法选择性地将拉伸应变施加到器件的沟道区，同时减轻所采用的掩模操作。 在半导体器件的NMOS和PMOS区上形成帽多晶硅层。 然后，使用抗蚀剂掩模从PMOS区域去除一部分盖多晶硅层。 随后，通过注入p型掺杂剂，采用相同的抗蚀剂掩模和/或盖多层的剩余部分在PMOS区内形成源/漏区。 之后，进行帽多晶热处理，其仅在位于NMOS区域内的器件的沟道区域中仅诱导拉伸应变。 结果，位于PMOS区域中的器件的沟道迁移率和/或性能基本上不劣化。

公开(公告)号：US20050090082A1

公开(公告)日：2005-04-28

申请号：US10695307

申请日：2003-10-28

申请人： Seetharaman Sridhar ,  Majid Mansoori

发明人： Seetharaman Sridhar ,  Majid Mansoori

IPC分类号： C30B1/00 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/66628 ,  H01L29/78

摘要： According to one embodiment of the invention, a method for forming MOSFETs includes providing a substrate having a source region, a gate region, and a drain region, forming a silicon-germanium layer in each of the source and drain regions, forming, in the substrate, a source in the source region and a drain in the drain region, forming a silicon layer outwardly from the silicon-germanium layer in each of the source and drain regions, and forming a silicide layer in each of the source and drain regions.

摘要翻译： 根据本发明的一个实施例，用于形成MOSFET的方法包括提供具有源极区域，栅极区域和漏极区域的衬底，在源极和漏极区域中的每一个中形成硅 - 锗层，在 源极区域中的源极和漏极区域中的漏极，在源极和漏极区域中的每一个中从硅 - 锗层向外形成硅层，并且在源极和漏极区域中的每一个中形成硅化物层。

公开(公告)号：US06617217B2

公开(公告)日：2003-09-09

申请号：US09967067

申请日：2001-09-28

申请人： Mahalingam Nandakumar ,  Dixit Kapila ,  Seetharaman Sridhar

发明人： Mahalingam Nandakumar ,  Dixit Kapila ,  Seetharaman Sridhar

IPC分类号： H01L21336

CPC分类号： H01L21/823892 ,  H01L21/76237 ,  H01L21/823878 ,  H01L27/0921

摘要： Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, and 60) the channeling of the subsequent zero degree implants is reduced.

摘要翻译： 通过植入氮化物膜（40）形成逆行井。 在STI（20）形成之后形成氮化物膜（40）。 通过在形成逆行井的部分（45,50,55和60）之后选择性地掩模具有光致抗蚀剂（47）的晶片的一部分，减少随后的零度植入物的引导。