公开(公告)号：US20050180019A1

公开(公告)日：2005-08-18

申请号：US10979624

申请日：2004-11-02

申请人： Gyoung Cho ,  Cheong Seo ,  Tae Kim

发明人： Gyoung Cho ,  Cheong Seo ,  Tae Kim

IPC分类号： G02B27/10

CPC分类号： G02B26/0833 ,  G02B27/2292 ,  G03B35/08 ,  G03B35/24 ,  H04N13/236 ,  H04N13/322 ,  H04N13/365

摘要： A three-dimensional (3-D) display system using a variable focal length lens includes at least one two-dimensional (2-D) display device, configured to display at least one two-dimensional image. The display system also includes an array of micromirror array lenses optically coupled to the display device, each micromirror array lens of the array of micromirror array lenses placed at a different location with respect to the display device, configured to focus the at least one two-dimensional image from each different location to provide a three-dimensional (3-D) image. The advantages of the present invention include increased viewing angles and wide depth range of three-dimensional images.

摘要翻译： 使用可变焦距透镜的三维（3-D）显示系统包括被配置为显示至少一个二维图像的至少一个二维（2-D）显示设备。 显示系统还包括光学耦合到显示装置的微镜阵列透镜的阵列，位于相对于显示装置的不同位置的微镜阵列透镜阵列的每个微镜阵列透镜，被配置为聚焦至少一个二维阵列， 来自每个不同位置的三维图像以提供三维（3-D）图像。 本发明的优点包括三维图像的增加的视角和宽的深度范围。

公开(公告)号：US20050170596A1

公开(公告)日：2005-08-04

申请号：US11024845

申请日：2004-12-30

申请人： Tae Kim

发明人： Tae Kim

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

摘要： A semiconductor device and a method for manufacturing the same are disclosed. A pattern of a polysilicon layer for a gate electrode and another pattern of a polysilicon layer for a resistor are respectively formed on an active region of a salicide region and a device isolation film of a non-salicide region by respectively interposing a gate insulating film between the one pattern and the active region and between the other pattern and the device isolation film. A spacer is then formed at sidewalls of the polysilicon layer for the gate electrode and a salicide prevention film is formed to encircle the polysilicon layer for the resistor. Subsequently, source and drain regions are formed on the active region of the salicide region and a salicide layer is formed on the gate electrode and the source and drain regions of the salicide region.

摘要翻译： 公开了一种半导体器件及其制造方法。 分别在非硅化物区域的有源区域和非硅化物区域的器件隔离膜上形成用于栅电极的多晶硅层的图案和用于电阻器的多晶硅层的另一图案， 一个图案和有源区域以及另一个图案和器件隔离膜之间。 然后在用于栅电极的多晶硅层的侧壁处形成间隔物，并且形成防止防硅膜以包围电阻器的多晶硅层。 随后，源极和漏极区形成在自对准硅化物区域的有源区上，并且在硅化物区域的栅极电极和源极和漏极区域上形成自对准硅化物层。

公开(公告)号：US20050135808A1

公开(公告)日：2005-06-23

申请号：US10913884

申请日：2004-08-05

申请人： Hyun Ho Yun ,  Tae Kim ,  Jeong Yoo ,  Byoung Kim

发明人： Hyun Ho Yun ,  Tae Kim ,  Jeong Yoo ,  Byoung Kim

IPC分类号： H04L12/28 ,  H04B10/20 ,  H04B10/24 ,  H04J14/02 ,  H04Q11/00

CPC分类号： H04J14/0282 ,  H04B10/40 ,  H04J14/02 ,  H04J14/0227 ,  H04J14/0241 ,  H04J14/0298 ,  H04Q11/0067 ,  H04Q2011/0016 ,  H04Q2011/0064

摘要： A termination device for use in a WDM-SCM PON system can effectively support a multi-channel integration function of a WDM/SCM PON system. The termination device contained in a termination end of a WDM/SCM (Wavelength Division Multiplexing/Sub-Carrier Multiplexing) PON (Passive Optical Network) to connect the PON with either a subscriber or an Ethernet service network includes: an Ethernet interface module connected to the Ethernet service network or the subscriber to perform an Ethernet interface function; a WDM/SCM physical layer module physically connected to the WDM/SCM PON to transmit/receive optical signals to/from the WDM/SCM PON; and a MAC (Media Access Control)-bridge module for performing a multiplexing/demultiplexing operation based on a MAC address upon receipt of transmission/reception frames, and reconstructing preambles of the frames while being classified according to channels so that individual Ethernet frames are matching-processed while being classified according to SCM channels of the WDM/SCM physical layer module.

摘要翻译： 用于WDM-SCM PON系统的终端设备可以有效地支持WDM / SCM PON系统的多信道集成功能。 包含在将PON与用户或以太网业务网络连接的WDM / SCM（波分复用/子载波复用）PON（无源光网络）的终端中的终端设备包括：以太网接口模块，连接到 以太网业务网络或用户执行以太网接口功能; WDM / SCM物理层模块，物理上连接到WDM / SCM PON以向/从WDM / SCM PON发送/接收光信号; 以及MAC（媒体访问控制） - 桥接模块，用于在接收到发送/接收帧时基于MAC地址执行复用/解复用操作，并且在根据信道分类的同时重构帧的前同步码，使得各个以太网帧匹配 在根据WDM / SCM物理层模块的SCM通道进行分类的过程中。

公开(公告)号：US20050102854A1

公开(公告)日：2005-05-19

申请号：US10958655

申请日：2004-10-06

申请人： Dong Lee ,  Il Han ,  Tae Kim

发明人： Dong Lee ,  Il Han ,  Tae Kim

IPC分类号： D06F58/04 ,  F26B11/02 ,  F26B25/00

CPC分类号： D06F58/04

摘要： A dryer rack for use with an apparatus for drying an object inside a drum is disclosed, wherein the dryer rack includes a platform for having an upper surface for supporting the object. The platform may include at least one grip for loading and unloading the dryer rack into an interior space of the drum. The at least one grip is flush with the upper surface of the platform. The at least one grip is formed in a forward portion of the platform, to be near an access point of the drum.

摘要翻译： 公开了一种与用于干燥滚筒内的物体的设备一起使用的烘干机架，其中干燥机架包括用于具有用于支撑物体的上表面的平台。 平台可以包括至少一个用于将干衣架装载和卸载到滚筒的内部空间中的把手。 至少一个手柄与平台的上表面齐平。 至少一个把手形成在平台的前部，靠近滚筒的接近点。

公开(公告)号：US20050095838A1

公开(公告)日：2005-05-05

申请号：US10880035

申请日：2004-06-29

申请人： Cheol Jeong ,  Tae Kim

发明人： Cheol Jeong ,  Tae Kim

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L21/76838 ,  H01L27/1052

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film and the second interlayer insulation film and contact to the contact plugs; forming a fourth interlayer insulation film over a resulting structure including the plurality of metal line patterns; forming a plurality of metal line contact holes by patterning the fourth interlayer insulation film; and forming a plurality of metal line contact plugs in the plurality of metal line contact holes by filling a metal material in the metal line contact holes.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：提供其上形成有多个导电区域的半导体衬底，其上形成有多个导电区域; 在半导体衬底上依次形成第一层间绝缘膜和第一蚀刻阻挡膜; 通过暴露形成在半导体衬底中的多个导电区域来形成多个接触孔，其中由于形成接触孔的工艺导致导电区域的杂质浓度降低; 在接触孔中填充金属材料并形成多个接触插塞; 在包括接触塞的所得结构上依次形成第二层间绝缘膜，第二蚀刻阻挡膜和第三层间绝缘膜; 形成多个金属线图案，其中所述金属线图案通过所述第三层间绝缘膜，所述第二蚀刻阻挡膜和所述第二层间绝缘膜并与所述接触插塞接触; 在包括所述多个金属线图案的所得结构上形成第四层间绝缘膜; 通过图案化第四层间绝缘膜形成多个金属线接触孔; 以及通过在金属线接触孔中填充金属材料在所述多个金属线接触孔中形成多个金属线接触塞。

公开(公告)号：US08737157B2

公开(公告)日：2014-05-27

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/00 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20120063256A1

公开(公告)日：2012-03-15

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/08 ,  H01L21/8239

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20110103158A1

公开(公告)日：2011-05-05

申请号：US13005453

申请日：2011-01-12

申请人： Tae Kim

发明人： Tae Kim

IPC分类号： G11C7/00 ,  G11C7/06

CPC分类号： G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20110098613A1

公开(公告)日：2011-04-28

申请号：US12909773

申请日：2010-10-21

申请人： Jonathan Thomas ,  John Pelochino ,  Akbar Dhanaliwala ,  Brian Krieger ,  Tae Kim

发明人： Jonathan Thomas ,  John Pelochino ,  Akbar Dhanaliwala ,  Brian Krieger ,  Tae Kim

IPC分类号： A61H1/00

CPC分类号： B25F5/02 ,  A61C17/221 ,  A61H7/005 ,  A61H19/40 ,  A61H23/0263 ,  A61H2201/0153 ,  A61H2201/5015 ,  A61H2201/5028 ,  A61H2201/5038 ,  A61H2201/5061 ,  A61H2201/5071 ,  A61H2201/5097

摘要： Provided are a system and method for controlling a device through changes in a pressure of a deformable chamber such as may be controlled by a user through a user's hand and/or body. In one example, a device with a deformable chamber detects pressure level changes from a baseline and modifies output parameters including modifications on the playback of stored patterns. In another example, a massage device with a deformable chamber records the most recent pressure level changes in a sequence, interprets the pressure level sequence as a sequence of power levels to a vibratory motor, and repeats back the interpretation until a further pressure input is received above a baseline. In another example, the massage device interprets the currently input sequence of pressure levels in real-time into a sequence of power levels delivered to the vibratory motor.

摘要翻译： 提供了一种用于通过可变形室的压力的变化来控制装置的系统和方法，诸如可以由用户通过使用者的手和/或身体来控制。 在一个示例中，具有变形室的装置检测来自基线的压力水平变化，并且修改输出参数，包括对所存储模式的回放的修改。 在另一示例中，具有可变形室的按摩装置记录序列中最近的压力水平变化，将压力水平序列解释为振动马达的功率水平序列，并重复解释，直到接收到另外的压力输入 高于基线。 在另一个示例中，按摩装置将当前输入的压力级别实时地解释为递送到振动马达的功率级的序列。

公开(公告)号：US07872923B2

公开(公告)日：2011-01-18

申请号：US12079765

申请日：2008-03-28

申请人： Tae Kim

发明人： Tae Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/08 ,  G11C5/148 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在存储器的有功断电状态期间，由于使用具有低阈值电压（Vth）的P和Nsense放大器用于数据信号的低Vcc感测，漏电流可能增加。 在Psense放大器控制线（例如ACT）和Vcc之间和/或在Nsense放大器控制线（例如RNL *）和Vss（地电位）之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能，但在有功掉电模式下导通，以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压，而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压，以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则，本摘要不应用于解释索赔。