利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

46 条记录 (耗时 0.017 秒)

    Integrated circuits with stress memory effect and fabrication methods thereof
    41.
    发明申请
    Integrated circuits with stress memory effect and fabrication methods thereof 有权
    具有应力记忆效应的集成电路及其制造方法

    公开(公告)号：US20080164530A1

    公开(公告)日：2008-07-10

    申请号：US11649282

    申请日：2007-01-04

    申请人： Mei-Yun Wang ,  Cheng-chen Hsueh ,  Wu-An Weng

    发明人： Mei-Yun Wang ,  Cheng-chen Hsueh ,  Wu-An Weng

    IPC分类号： H01L27/088 ,  H01L21/77

    CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/7843

    摘要： Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

    摘要翻译： 具有选择性应力记忆效应的半导体器件及其制造方法。 半导体器件包括具有第一区域和第二区域的半导体衬底。 第一区域和第二区域都具有由绝缘层隔开的第一掺杂区域和第二掺杂区域。 PMOS晶体管设置在第一掺杂区域层上。 NMOS晶体管设置在第二掺杂区域上。 第一覆盖层被设置为在第一区域上覆盖NMOS晶体管。 在第一区域上设置覆盖PMOS晶体管的第二覆盖层。 第一覆盖层的厚度与第二覆盖层的厚度不同，因此在PMOS晶体管和NMOS晶体管上分别产生不同的应力。 在第二区域上的PMOS晶体管和NMOS晶体管被硅化。

    One step dual salicide formation for ultra shallow junction applications
    42.
    发明授权
    One step dual salicide formation for ultra shallow junction applications 有权
    超浅结合应用的一步双重自杀化合物形成

    公开(公告)号：US06589836B1

    公开(公告)日：2003-07-08

    申请号：US10263896

    申请日：2002-10-03

    申请人： Mei-Yun Wang ,  Chih-Wei Chang

    发明人： Mei-Yun Wang ,  Chih-Wei Chang

    IPC分类号： H01L218238

    CPC分类号： H01L21/823835 ,  H01L21/823814

    摘要： A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS device, has been developed. The process features the implantation of metal ions such as titanium, tantalum, vanadium, or rhenium, during the implantation procedure used for formation of the heavily doped P type source/drain region of the PMOS device. The presence of the implanted metal ions in PMOS regions retard the formation of metal silicide resulting in a thinner metal silicide layer on the heavily doped P type source/drain region, when compared to the thicker metal silicide counterparts simultaneously formed on elements of the NMOS device. The thinner metal silicide for the PMOS device reduces the risk of junction leakage at the heavily doped P type source/drain—N well interface, while the thicker metal silicide layer located on elements of the NMOS device, allow lower word line resistance to be realized.

    摘要翻译： 用于在NMOS器件的元件和PMOS器件的元件上形成金属硅化物的工艺，其中形成在PMOS器件的元件上的金属硅化物比同时形成在所述NMOS器件的元件上的金属硅化物更薄，已被开发 。 在用于形成PMOS器件的重掺杂P型源极/漏极区域的植入过程期间，该工艺的特征在于金属离子如钛，钽，钒或铼的注入。 与在NMOS器件的元件上同时形成的较厚的金属硅化物对应物相比，在PMOS区域中注入的金属离子的存在延迟了金属硅化物的形成，导致在重掺杂的P型源极/漏极区域上的较薄的金属硅化物层 。 用于PMOS器件的较薄金属硅化物降低了在重掺杂P型源极/漏极-N阱界面处的结漏电的危险，而位于NMOS器件元件上的较厚金属硅化物层允许实现较低的字线电阻 。

    Multi-step deposition to improve the conformality of ionized PVD films
    43.
    发明授权
    Multi-step deposition to improve the conformality of ionized PVD films 失效
    多步沉积以提高离子化PVD膜的一致性

    公开(公告)号：US6077779A

    公开(公告)日：2000-06-20

    申请号：US083274

    申请日：1998-05-22

    申请人： Shaulin Shue ,  Mei-Yun Wang

    发明人： Shaulin Shue ,  Mei-Yun Wang

    IPC分类号： C23C14/04 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/3492 ,  H01L21/2855 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002

    摘要： Methods are disclosed to provide a low-cost method of producing a refractory liner in submicron vias or trenches applying ionized metal plasma using physical vapor deposition (PVD). The refractory liner is deposited on the bottom and sidewalls of the submicron vias and trenches in a two step PVD, using first high pressure and then low pressure. By selecting adhesion layer and diffusion barrier materials such as tantalum, tantalum nitride or titanium nitride or alloys of these metals a uniform barrier is created which forms a suitable layer around copper metallization.

    摘要翻译： 公开了提供一种在使用物理气相沉积（PVD）应用电离金属等离子体的亚微米通孔或沟槽中制造耐火材料衬里的低成本方法。 使用第一高压然后低压将耐火材料衬里沉积在亚微米通孔和沟槽的底部和侧壁上的两步PVD中。 通过选择粘合层和扩散阻挡材料如钽，氮化钽或氮化钛或这些金属的合金，产生均匀的屏障，其形成围绕铜金属化的合适的层。

    Method for fabricating semiconductor device with silicided gate
    45.
    发明申请
    Method for fabricating semiconductor device with silicided gate 有权
    用硅化物栅极制造半导体器件的方法

    公开(公告)号：US20080261394A1

    公开(公告)日：2008-10-23

    申请号：US11787842

    申请日：2007-04-18

    申请人： Mei-Yun Wang ,  Cheng-Chen Calvin Hsueh

    发明人： Mei-Yun Wang ,  Cheng-Chen Calvin Hsueh

    IPC分类号： H01L21/44 ,  H01L21/8238

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.

    摘要翻译： 一种用于制造半导体器件的方法，该半导体器件具有硅化物栅极，其被引导以形成硅化物结构，同时保持栅极 - 电介质完整性。 最初，栅极结构优选地具有通过栅极电介质从衬底分离的多晶硅栅极，然后在至少多晶硅栅极上沉积金属层。 制造环境放置在高温下。 栅极结构可以是包括在诸如CMOS器件的双栅极器件中的两个栅极结构之一，在这种情况下，各个栅极可以形成在不同的高度（厚度），以确保硅化物形成适当的相位。 源极和漏极区域也优选是硅化的，但是在通过例如光致抗蚀剂或硬掩模结构的盖保护栅电极的同时进行的单独工艺。