公开(公告)号：US08168485B2

公开(公告)日：2012-05-01

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US20100032730A1

公开(公告)日：2010-02-11

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US20090269908A1

公开(公告)日：2009-10-29

申请号：US12385782

申请日：2009-04-20

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L21/04

CPC分类号： H01L29/47 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

摘要： A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

摘要翻译： 半导体器件的制造方法包括在碳化硅衬底中掺杂导电杂质的工艺，在碳化硅衬底的表面上形成覆盖层的工艺，激活掺杂在碳化硅衬底中的导电杂质的工艺， 在第一退火工艺之后氧化盖层的工艺，以及去除氧化的盖层的工艺。 优选的是，盖层由包括金属碳化物的材料形成。 由于金属碳化物的氧化开始温度相对较低，如果在盖层中包括金属碳化物，则盖层的氧化变得容易。 具体而言，优选由碳化钽等氧化开始温度为1000℃以下的金属碳化物形成盖层。

公开(公告)号：US08324704B2

公开(公告)日：2012-12-04

申请号：US12659853

申请日：2010-03-23

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L29/47 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

摘要： A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

摘要翻译： 具有肖特基势垒二极管的碳化硅半导体器件包括第一导电型碳化硅衬底，在衬底的第一表面上的第一导电型碳化硅漂移层，与漂移层形成肖特基接触的肖特基电极和欧姆 电极在基板的第二表面上。 肖特基电极包括与漂移层直接接触的氧化物层。 氧化物层由钼，钛，镍或这些元素中的至少两种的合金的氧化物制成。

公开(公告)号：US20080239817A1

公开(公告)日：2008-10-02

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/10

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。