公开(公告)号：US20080239817A1

公开(公告)日：2008-10-02

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/10

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。

公开(公告)号：US07796442B2

公开(公告)日：2010-09-14

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/04

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。

公开(公告)号：US10020390B2

公开(公告)日：2018-07-10

申请号：US15107313

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L21/265

CPC分类号： H01L29/7811 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

公开(公告)号：US09780205B2

公开(公告)日：2017-10-03

申请号：US15104332

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

公开(公告)号：US09136372B2

公开(公告)日：2015-09-15

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

公开(公告)号：US20140252465A1

公开(公告)日：2014-09-11

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US20120012860A1

公开(公告)日：2012-01-19

申请号：US13177747

申请日：2011-07-07

申请人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

发明人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7828

摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.

摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。 源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。 接触孔沿第一方向具有纵向方向。

公开(公告)号：US09024330B2

公开(公告)日：2015-05-05

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

发明人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US08710586B2

公开(公告)日：2014-04-29

申请号：US13229892

申请日：2011-09-12

申请人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/66 ,  H01L29/15

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

摘要翻译： SiC半导体器件包括：依次堆叠的衬底，漂移层和基极区域; 第一和第二源极区域和基极区域中的接触层; 穿透源区和基区的沟槽; 沟槽中的栅电极; 具有覆盖所述栅电极的接触孔的层间绝缘膜; 源极通过接触孔与源极区域和接触层耦合; 衬底上的漏电极; 和金属硅化物膜。 高浓度第二源区比低浓度第一源区浅，并且具有被层间绝缘膜覆盖的部分，其包括表面附近的低浓度第一部分和比第一部分更深的高浓度第二部分。 第二部分上的金属硅化物膜的厚度大于第一部分。