公开(公告)号：US07454575B2

公开(公告)日：2008-11-18

申请号：US10583773

申请日：2004-12-21

申请人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Shuji Miyasaka

发明人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Shuji Miyasaka

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0886 ,  G06F12/127

摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.

摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。

公开(公告)号：US20080059203A1

公开(公告)日：2008-03-06

申请号：US11597558

申请日：2005-09-13

申请人： Mineo Tsushima ,  Yoshiaki Takagi ,  Kojiro Ono ,  Naoya Tanaka ,  Shuji Miyasaka

发明人： Mineo Tsushima ,  Yoshiaki Takagi ,  Kojiro Ono ,  Naoya Tanaka ,  Shuji Miyasaka

IPC分类号： G10L19/00

CPC分类号： G10L19/0208 ,  G10L19/008

摘要： Provided are an audio encoding device and an audio decoding device, by which optimal trade-off between code rates and sound quality can be flexibly adjusted. A variable frequency segmentation encoding unit (110) has: difference degree calculation units (101, 102, and 103) for calculating a difference degree between the first and second input signals, depending on a segmentation method A, B, or C for segmenting a frequency band into sub-bands; a selection unit (104) for selecting one of the segmentation methods; and a difference degree and segmentation information encoding unit (105) for encoding the selected method and the difference degree for each sub-band by the method. A variable frequency segment decoding unit (210) has: a segmentation information decoding unit 202 for decoding the segmentation information to learn the segmentation method; a switching unit (203) for outputting a difference degree code to one of difference degree decoding units corresponding to the segmentation method; and difference degree decoding units (204, 205, and 206), for decoding the difference degree code to the difference degree for each sub-band.

摘要翻译： 提供了一种音频编码装置和音频解码装置，可以灵活地调整码率和声音质量之间的最佳权衡。 可变频率分割编码单元（110）具有：用于计算第一和第二输入信号之间的差值的差分计算单元（101,102和103），这取决于分段方法A，B或C，用于分割 频带变成子带; 选择单元（104），用于选择所述分割方法之一; 以及用于通过该方法对所选择的方法和每个子带的差分度进行编码的差分度和分割信息编码单元（105）。 可变频段解码单元（210）具有：分割信息解码单元202，对分割信息进行解码以学习分割方法; 切换单元，用于将差分度码输出到与分割方法对应的差分度解码单元之一; 和差分度解码单元（204,205和206），用于将差分度码解码为每个子带的差分度。

公开(公告)号：US20070255572A1

公开(公告)日：2007-11-01

申请号：US11660094

申请日：2005-08-02

申请人： Shuji Miyasaka ,  Yoshiaki Takagi ,  Naoya Tanaka ,  Mineo Tsushima

发明人： Shuji Miyasaka ,  Yoshiaki Takagi ,  Naoya Tanaka ,  Mineo Tsushima

IPC分类号： G10L19/00

CPC分类号： G10L19/008 ,  H04S3/00

摘要： An audio decoder which reproduces original signals from a bit stream including a downmix signal of the original signals and supplementary information indicating the gain ratio D and the phase difference θ between the original signals. The audio decoder which reproduces the original signals includes: a decoding unit (100) which extracts the downmix signal from the bitstream; a transformation unit (101) which transforms the extracted downmix signal into a frequency domain signal; a phase rotator determination unit (102) which determines two phase rotators having, as the phase rotation angles, angles α and β respectively obtained by dividing a contained angle by a diagonal of a parallelogram where the length ratio of two adjacent sides equals to the gain ratio D and the contained angle equals to the phase difference θ, a separation unit (103) which separates the frequency domain signal into two separation signals respectively indicating angles α and β as phase differences between the signals and the decoded downmix signal, and an inverse transformation unit (104) which inversely transforms the respective two separation signals into time domain signals so as to reproduce the two audio signals.

摘要翻译： 一种音频解码器，其从包括原始信号的下混信号的比特流中再现原始信号，以及指示增益比D和原始信号之间的相位差θ的补充信息。 再现原始信号的音频解码器包括：解码单元（100），其从比特流中提取降混信号; 变换单元，其将所提取的下混信号变换为频域信号; 相位旋转器确定单元（102），其确定两个相位旋转器，其具有作为相位旋转角度的角度α和β，分别通过将包含的角度除以两个相邻边的长度比等于增益的平行四边形的对角线获得 比率D和包含的角度等于相位差θ，分离单元（103）将频域信号分离成分别表示角度α和β的两个分离信号，作为信号和解码的下混信号之间的相位差，以及反相 变换单元（104），其将相应的两个分离信号逆变换为时域信号，以便再现两个音频信号。

公开(公告)号：US06484142B1

公开(公告)日：2002-11-19

申请号：US09551796

申请日：2000-04-18

申请人： Shuji Miyasaka ,  Takeshi Norimatsu ,  Mineo Tsushima ,  Tomokazu Ishikawa ,  Yoshiaki Sawada

发明人： Shuji Miyasaka ,  Takeshi Norimatsu ,  Mineo Tsushima ,  Tomokazu Ishikawa ,  Yoshiaki Sawada

IPC分类号： G10L1914

CPC分类号： H03M7/42

摘要： An encoder of the present invention includes: G storage sections for storing G groups of data; a selection section for selecting one of H Huffman codebooks having codebook numbers for each of the groups of data; G encoding sections Huffman-encoding the G groups of data by using the selected Huffman codebook; and an encoding section for encoding the codebook number of each Huffman codebook selected. The selection section includes a calculation section for calculating a code length and a control section for selecting one of the Huffman codebooks. When the Huffman codebook selected is an unsigned codebook, a number of bits required for sign information has previously been added to the calculated code length.

摘要翻译： 本发明的编码器包括：G存储部分，用于存储G组数据; 选择部分，用于选择具有每组数据的码本号码的霍夫曼代码簿之一; G编码部分通过使用所选的霍夫曼码本对G组数据进行霍夫曼编码; 以及编码部，用于编码所选择的每个霍夫曼码本的码本号。 选择部分包括用于计算代码长度的计算部分和用于选择霍夫曼码本之一的控制部分。 当选择的霍夫曼代码簿是无符号码本时，已经将计算的代码长度添加到符号信息所需的位数。

公开(公告)号：US08311841B2

公开(公告)日：2012-11-13

申请号：US11806971

申请日：2007-06-05

申请人： Shuji Miyasaka ,  Tomokazu Ishikawa ,  Yoshiaki Sawada

发明人： Shuji Miyasaka ,  Tomokazu Ishikawa ,  Yoshiaki Sawada

IPC分类号： G10L19/00 ,  G10L21/04

CPC分类号： G10L19/18 ,  G10L19/24

摘要： A decoding device (30a) comprises a narrow-band decoding unit (31) operable to reproduce a PCM signal (P1) from a narrow-band bit stream included in a wide-band bit stream (S0), a wide-band decoding unit (32) operable to reproduce a PCM signal (P2) having a frequency band which is wider than that of the PCM signal (P1) reproduced by the narrow-band decoding unit (31) from the narrow-band bit stream and a band expanding bit stream included in the wide band bit stream (S0) and a selecting unit (34) operable to select either the PCM signal (P1) reproduced by the narrow-band decoding unit (31) or the PCM signal (P2) reproduced by the wide-band decoding unit (32), and to output the selected sound digital signal.

摘要翻译： 解码装置（30a）包括：窄带解码单元，用于从包括在宽带比特流（S0）中的窄带比特流中再现PCM信号（P1）;宽带解码单元 （32），用于从窄带位流再现具有比由窄带解码单元（31）再现的PCM信号（P1）的频带宽的频带的PCM信号（P2） 包括在宽带比特流（S0）中的比特流和选择单元（34）可操作以选择由窄带解码单元（31）再现的PCM信号（P1）或由 宽带解码单元（32），并输出所选择的声音数字信号。

公开(公告)号：US08151254B2

公开(公告)日：2012-04-03

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

摘要翻译： 提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。 操作者定义文件102包括通过类定义的各种定点类型操作符的定义。 编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。 编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130， 执行针对包括替代机器语言指令的中间代码的优化。

公开(公告)号：US20120039397A1

公开(公告)日：2012-02-16

申请号：US13281002

申请日：2011-10-25

申请人： Hiroshi IKEDA ,  Shuji Miyasaka

发明人： Hiroshi IKEDA ,  Shuji Miyasaka

IPC分类号： G10L21/00 ,  H04N7/26

CPC分类号： H04N5/783 ,  G10L25/78 ,  H04N5/93 ,  H04N21/4325 ,  H04N21/4394 ,  H04N21/4402

摘要： A digital signal reproduction device includes an audio decoder configured to decode an audio bit stream to output a resulting audio signal, an audio bit stream analyzer configured to analyze whether or not the audio bit stream contains human voice, a playback speed determiner configured to determine a playback speed based on a result of the analysis by the audio bit stream analyzer, and a variable speed reproducer configured to receive the audio signal and reproduce an audio signal corresponding to the playback speed determined by the playback speed determiner.

摘要翻译： 一种数字信号再现装置，包括：音频解码器，被配置为对音频比特流进行解码以输出所得到的音频信号;音频比特流分析器，被配置为分析音频比特流是否包含人声;回放速度确定器， 基于音频比特流分析器的分析结果的播放速度以及被配置为接收音频信号并再现与由重放速度确定器确定的播放速度相对应的音频信号的可变速度再现器。

公开(公告)号：US20070271095A1

公开(公告)日：2007-11-22

申请号：US11659949

申请日：2005-08-18

申请人： Shuji Miyasaka ,  Yoshiaki Takagi ,  Naoya Tanaka ,  Mineo Tsushima

发明人： Shuji Miyasaka ,  Yoshiaki Takagi ,  Naoya Tanaka ,  Mineo Tsushima

IPC分类号： G10L19/00 ,  G10L19/02 ,  H03M7/30

CPC分类号： G11B27/022 ,  G10L19/008 ,  G11B20/00007

摘要： An audio encoder, which is capable of encoding multiple-channel signals so that only a downmixed signal is decoded and of further generating specific auxiliary information necessary for dividing the downmixed signal, is provided. An audio encoder (10), which compresses and encodes audio signals of N-channels (N>1), includes a downmixed signal encoding unit (11) which encodes the downmixed signal obtained by downmixing the audio signals, and an auxiliary information generation unit (12a) which generates auxiliary information necessary for decoding the downmixed signal encoded by the downmixed signal encoding unit (11) into N-channel audio signals. The auxiliary information generation unit (12a) includes transformation units (121) and (122) which transform audio signals respectively into frequency domain signals, a detection unit (123) which detects phase difference information and gain ratio information each indicates a degree of difference between frequency domain signals, and a quantization unit (125) which quantizes, for each frequency band, the phase difference information and gain ratio information detected by the detection unit (123) using the quantization precision setting table (124). The quantization precision setting table (124) functions as a division unit which divides a frequency band of a frequency domain signal into plural sub-bands.

摘要翻译： 一种音频编码器，其能够对多声道信号进行编码，使得只下降混合信号被解码，并且进一步产生分割下混合信号所需的特定辅助信息。 对N声道（N> 1）的音频信号进行压缩编码的音频编码器（10）包括下混合信号编码单元（11），其对通过降低音频信号而获得的下混合信号进行编码，以及辅助信息生成单元 （12a），其产生将由下混合信号编码单元（11）编码的下混合信号解码成N声道音频信号所需的辅助信息。 辅助信息生成单元（12a）包括将音频信号分别变换为频域信号的变换单元（121）和（122），检测单元（123），其检测相位差信息，增益比信息各自表示差异度 和量化单元（125），其对于每个频带，使用量化精度设定表（124）对由检测单元（123）检测的相位差信息和增益比信息进行量化。 量化精度设定表（124）作为将频域信号的频带划分为多个子带的分割单位起作用。

公开(公告)号：US20070256065A1

公开(公告)日：2007-11-01

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

公开(公告)号：US07185176B2

公开(公告)日：2007-02-27

申请号：US10449788

申请日：2003-06-02

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

IPC分类号： G06F15/80

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。