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公开(公告)号：US09531394B1
公开(公告)日：2016-12-27
申请号：US14745545
申请日：2015-06-22
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost
CPC classification number: H03L7/091 , G06F1/022 , H03K5/135 , H03L7/081 , H03L7/0814 , H03L7/0891 , H03L7/093 , H03L7/183 , H03L7/1976
Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
Abstract translation: 用于校准数字 - 时间转换器的技术包括一种包括数字 - 时间转换器的装置，其被配置为基于数字码，输入信号和增益校准信号来产生输出信号。 输出信号具有基于数字码从输入信号的相应边缘线性延迟的边缘。 数字代码在评估代码和校准代码之间摇摆。 该装置包括被配置为提供输入信号的延迟版本的参考信号发生器。 参考信号发生器的延迟与数字 - 时间转换器的延迟相匹配。 该装置包括校准电路，其被配置为基于输出信号和输入信号的延迟版本来生成增益校准信号。 校准代码可以在第一校准延迟代码和第二校准延迟代码之间交替。
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公开(公告)号：US20160351309A1
公开(公告)日：2016-12-01
申请号：US14722607
申请日：2015-05-27
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee
CPC classification number: H03B5/00 , H01F17/0013 , H01F2017/0073 , H01F2017/0086 , H03B2200/0016
Abstract: A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.
Abstract translation: 已经公开了一种用于降低电感器系统的串联电阻的技术，其可以增加电感器系统的品质因数。 一种装置包括由第一导电层形成的导电回路。 导电回路包括第一端子和第二端子。 第一端子包括在第一导电层中的至少一个第一导电指状物。 第二端子包括在第一导电层中的至少一个第二导电指状物。 所述至少一个第二导电指状物与所述至少一个第一导电指状物交错，而不直接接触所述至少一个第一导电指状物。 该装置可以包括在第一导电层中的蛇形间隙。 该装置可以包括分别耦合到第二导电层并且分别耦合至少一个第一导电指状物的至少一个第一导电通孔。
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Patent Agency Ranking
公开(公告)号：US09379879B1
公开(公告)日：2016-06-28
申请号：US14817129
申请日：2015-08-03
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , James F. Parker
CPC classification number: G04F10/005 , H03L7/091 , H03L7/23 , H03L2207/50
Abstract: A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.
Abstract translation: 噪声整形时间 - 数字转换器具有大范围和高分辨率。 时间数字转换器包括相位检测器，其被配置为基于相位调整反馈信号和输入信号产生相位误差信号。 该时间 - 数字转换器包括环路滤波器，其被配置为对相位误差信号进行积分并产生模拟积分相位误差信号。 时间 - 数字转换器包括被配置为将模拟积分相位误差信号转换为数字相位误差代码的模拟 - 数字转换器。 时间 - 数字转换器包括数字 - 时间转换器，其被配置为基于参考信号和使能信号将数字相位误差代码的至少一部分转换为门控信号。 该时间 - 数字转换器包括基于参考信号和门控信号产生相位调整反馈信号的反馈电路。
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公开(公告)号：US09369138B1
公开(公告)日：2016-06-14
申请号：US14745545
申请日：2015-06-22
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost
Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
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公开(公告)号：US09356606B2
公开(公告)日：2016-05-31
申请号：US14339113
申请日：2014-07-23
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
CPC classification number: H03B5/12 , H03B1/00 , H03B5/36 , H03L1/026 , H03L7/02 , H03L7/183 , H03L7/1976
Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.
Abstract translation: 时钟发生器包括自由振荡器和可调频率合成器。 自由振荡器具有用于提供振荡器时钟信号的输出。 可调谐频率合成器耦合到自由振荡器，并响应振荡器时钟信号和频率控制信号提供时钟输出信号。 频率控制信号对应于自由振荡器的测量特性。
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公开(公告)号：US20160028405A1
公开(公告)日：2016-01-28
申请号：US14339113
申请日：2014-07-23
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
CPC classification number: H03B5/12 , H03B1/00 , H03B5/36 , H03L1/026 , H03L7/02 , H03L7/183 , H03L7/1976
Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.
Abstract translation: 时钟发生器包括自由振荡器和可调频率合成器。 自由振荡器具有用于提供振荡器时钟信号的输出。 可调谐频率合成器耦合到自由振荡器，并响应振荡器时钟信号和频率控制信号提供时钟输出信号。 频率控制信号对应于自由振荡器的测量特性。
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公开(公告)号：US20150091537A1
公开(公告)日：2015-04-02
申请号：US14040839
申请日：2013-09-30
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.
Abstract translation: 公开了使用热敏电阻的参考信号发生器。 一种装置包括具有第一温度系数的第一装置和具有与第一温度系数相反的符号的第二温度系数的热敏电阻。 电路维持第一信号和第二信号的等效，并且利用热敏电阻的第二温度变化来抵消第一装置的第一温度变化，以产生具有低温度系数的第二信号。 第一器件可以是被配置为产生基极 - 发射极电压并与热敏电阻串联耦合的双极晶体管。 第一信号可以是第一节点上的第一电压。 第二信号可以是第二节点上的第二电压。 电路可以被配置为保持第一电压和第二电压的有效等效。 该装置可以包括耦合到第二节点的电阻器。
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