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    Methods for scheduling read and write commands and apparatuses using the same
    41.
    发明授权
    Methods for scheduling read and write commands and apparatuses using the same 有权

    公开(公告)号：US09971546B2

    公开(公告)日：2018-05-15

    申请号：US15220739

    申请日：2016-07-27

    Applicant: Silicon Motion, Inc.

    Inventor： Yang-Chih Shen

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

    Abstract: A method for scheduling read and write commands, performed by a processing unit, including at least the following steps: the processing unit obtains more than one read commands from a read queue successively and executes the obtained read commands until a first condition is met. After the first condition is met, the processing unit obtains more than one write commands from a write queue successively and executes the obtained write commands until a second condition is met.

    Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same
    42.
    发明申请
    Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same 审中-公开

    公开(公告)号：US20170357590A1

    公开(公告)日：2017-12-14

    申请号：US15689767

    申请日：2017-08-29

    Applicant: Silicon Motion, Inc.

    Inventor： Yang-Chih Shen ,  Che-Wei Hsu

    IPC: G06F12/0873

    CPC classification number: G06F12/0873 ,  G06F2212/1021 ,  G06F2212/313 ,  G06F2212/608

    Abstract: The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.

    Flash memory controller
    44.
    发明申请
    Flash memory controller 有权

    公开(公告)号：US20160351255A1

    公开(公告)日：2016-12-01

    申请号：US15235128

    申请日：2016-08-12

    Applicant: Silicon Motion Inc.

    Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

    IPC: G11C11/56

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

    Methods for Reading Data from a Storage Unit of a Flash Memory and Apparatuses Using the Same
    45.
    发明申请
    Methods for Reading Data from a Storage Unit of a Flash Memory and Apparatuses Using the Same 有权
    从闪存的存储单元读取数据的方法及其使用方法

    公开(公告)号：US20160239416A1

    公开(公告)日：2016-08-18

    申请号：US14702392

    申请日：2015-05-01

    Applicant: Silicon Motion, Inc.

    Inventor： Yang-Chih Shen

    IPC: G06F12/08

    CPC classification number: G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7203

    Abstract: A method for reading data from a storage unit of a flash memory, performed by a processing unit, including at least the following steps: A first read command is received from a master device via a first access interface. It is determined whether data requested by the first read command has been cached in a first buffer, which caches continuous data obtained from a storage unit. A second access interface is directed to read the data requested by the first read command from the storage unit and store the read data in a second buffer and the first access interface is directed to read the data requested by the first read command from the second buffer and clock the read data out to the master device when data requested by the first read command has not been cached in the first buffer.

    Abstract translation: 一种从处理单元执行的从闪存存储单元读取数据的方法，至少包括以下步骤：经由第一访问接口从主设备接收第一读命令。 确定由第一读取命令请求的数据是否已被缓存在第一缓冲器中，该缓冲器缓存从存储单元获取的连续数据。 第二访问接口旨在从存储单元读取由第一读取命令请求的数据，并将读取的数据存储在第二缓冲器中，并且第一访问接口被指示从第二缓冲器读取由第一读取命令请求的数据 并且当第一读取命令请求的数据没有被缓存在第一缓冲器中时，将读取的数据输出到主设备。

    Flash memory controller
    46.
    发明申请
    Flash memory controller 有权
    闪存控制器

    公开(公告)号：US20160110133A1

    公开(公告)日：2016-04-21

    申请号：US14983566

    申请日：2015-12-30

    Applicant: Silicon Motion Inc.

    Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

    Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

    Data Storage Device and Data Maintenance Method Thereof
    47.
    发明申请
    Data Storage Device and Data Maintenance Method Thereof 有权
    数据存储设备及其数据维护方法

    公开(公告)号：US20160103734A1

    公开(公告)日：2016-04-14

    申请号：US14711472

    申请日：2015-05-13

    Applicant: Silicon Motion, Inc.

    Inventor： Ching-Ke Chen ,  Po-Sheng Chou ,  Yang-Chih Shen

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G11C29/52 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G11C2029/0411

    Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.

    Abstract translation: 一种包括闪存和控制器的数据存储设备。 闪速存储器包括多个芯片，每个芯片包括多个页面，页面被布置成组合成超块，超块的页面从超级块的顶部到底部编号为0〜X， 编号为0〜Y-1的页面构成数据区域，数字Y〜X的页面构成RAID奇偶校验区域。 当数据区中的数据无法成功读取时，控制器会根据RAID奇偶校验区域的数据来校正数据区的数据。

    Flash memory controller
    48.
    发明授权
    Flash memory controller 有权

    公开(公告)号：US11914873B2

    公开(公告)日：2024-02-27

    申请号：US17324121

    申请日：2021-05-19

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

    IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

    CPC classification number: G06F3/0634 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5642 ,  G06F2212/7201 ,  G06F2212/7206 ,  Y02D10/00

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

    Flash memory controller
    49.
    发明申请
    Flash memory controller 审中-公开

    公开(公告)号：US20200081641A1

    公开(公告)日：2020-03-12

    申请号：US16686200

    申请日：2019-11-17

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

    IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

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