公开(公告)号：US20110197033A1

公开(公告)日：2011-08-11

申请号：US13087974

申请日：2011-04-15

申请人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

发明人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/0835 ,  G06F12/12

摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

摘要翻译： 在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

公开(公告)号：US20100293401A1

公开(公告)日：2010-11-18

申请号：US12465182

申请日：2009-05-13

申请人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

发明人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

IPC分类号： G06F1/32

CPC分类号： G06F1/3228 ,  G06F9/526

摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。

公开(公告)号：US20100235675A1

公开(公告)日：2010-09-16

申请号：US12787865

申请日：2010-05-26

申请人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

发明人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC分类号： G06F13/14 ,  G06F1/04 ,  G06F13/362

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US07512129B1

公开(公告)日：2009-03-31

申请号：US10299236

申请日：2002-11-18

申请人： John G. Favor ,  Edmund G. Chen ,  Ruchi Wadhawan

发明人： John G. Favor ,  Edmund G. Chen ,  Ruchi Wadhawan

IPC分类号： H04L12/28 ,  H04J3/24

CPC分类号： H04L49/9094 ,  H04L49/557 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

摘要： A method and apparatus for processing out-of-order processing of packets is described. In one embodiment, the method includes receiving a packet, which is in an original position relative to other packets; and attempting, by a primary processing unit, to classify and process the packet. The method also includes determining whether the packet was completely classified and processed by the primary processing unit; and upon determining that the primary processing unit completely classified and processed the packet, bypassing a secondary processing unit. The method also includes transmitting the packet onto a network, the packet being transmitted in its original position relative to the other packets.

摘要翻译： 描述了用于处理分组的无序处理的方法和装置。 在一个实施例中，该方法包括接收相对于其他分组处于原始位置的分组; 并且由主处理单元尝试对分组进行分类和处理。 该方法还包括确定分组是否被主处理单元完全分类和处理; 并且一旦确定所述主处理单元完全对所述分组进行了分类和处理，则绕过所述辅助处理单元。 该方法还包括将分组发送到网络上，该分组相对于其他分组在其原始位置被发送。

公开(公告)号：US07496695B2

公开(公告)日：2009-02-24

申请号：US11238790

申请日：2005-09-29

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US07461190B2

公开(公告)日：2008-12-02

申请号：US11201581

申请日：2005-08-11

申请人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

发明人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US20080259928A1

公开(公告)日：2008-10-23

申请号：US12054235

申请日：2008-03-24

申请人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

发明人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

IPC分类号： H04L12/56

CPC分类号： H04L49/9094 ,  H04L49/90

摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.

摘要翻译： 将参照具体实施方式和附图更好地描述本发明的这些和其它方面。 描述了使用链表对包进行无序处理的方法和装置。 在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。 该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。 该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于 全球秩序。 该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

公开(公告)号：US20070073922A1

公开(公告)日：2007-03-29

申请号：US11238790

申请日：2005-09-29

申请人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

公开(公告)号：US06256320B1

公开(公告)日：2001-07-03

申请号：US09087104

申请日：1998-05-29

申请人： Wen-Tsung Tang ,  Ruchi Wadhawan

发明人： Wen-Tsung Tang ,  Ruchi Wadhawan

IPC分类号： H04J302

CPC分类号： H04L12/44 ,  H04J3/0685 ,  H04L12/413

摘要： A distributed arbitration scheme for a network. Ports in a network device determine which port in a set of ports may broadcast a packet onto a bus in the network device. A method of transmitting data between a set of ports sharing a bus in hub is described. The set of ports includes a first port, and the method comprises the first port receiving a packet, the first port requesting the bus, and, if another port is requesting the bus, the first port transmitting the packet to the bus if the first port has not transmitted a packet later than the another port requesting the bus. A system using two clocks of different speeds in a network device. The hub has at least a port. The port has an internal data path having a first width. A bus is coupled to the port. The bus has a data path that has a second width. The second width is greater than the first width. The hub includes a first clock that has a first frequency and is coupled to circuitry in the port for clocking internal data transfers. The hub includes a second clock that has a second frequency less than the first frequency, and the second clock is coupled to circuitry in the port for qualifying data transfers with the bus.

摘要翻译： 网络的分布式仲裁方案。 网络设备中的端口确定一组端口中的哪个端口可以在网络设备中的总线上广播分组。 描述了在集线器中共享总线的一组端口之间传输数据的方法。 所述端口组包括第一端口，并且所述方法包括：接收分组的第一端口，请求总线的第一端口，以及如果另一端口正在请求总线，则第一端口将总线发送到总线，如果第一端口 没有比另一个请求总线的端口发送一个数据包。 在网络设备中使用不同速度的两个时钟的系统。 集线器至少有一个端口。 端口具有第一宽度的内部数据路径。 总线连接到端口。 总线具有第二宽度的数据路径。 第二宽度大于第一宽度。 集线器包括具有第一频率的第一时钟并且耦合到端口中用于计时内部数据传输的电路。 集线器包括具有小于第一频率的第二频率的第二时钟，并且第二时钟耦合到端口中的电路以用于与总线进行数据传输的限定。

公开(公告)号：US06192071B1

公开(公告)日：2001-02-20

申请号：US08994519

申请日：1997-12-19

申请人： Ryan E. Hirth ,  Ruchi Wadhawan

发明人： Ryan E. Hirth ,  Ruchi Wadhawan

IPC分类号： H03H730

CPC分类号： H04L25/03885

摘要： A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, one embodiment also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude. One embodiment corrects for offsets that may get superimposed on the signal as it passes through the receive channel and which may lead to erroneous bit decisions. The method is applicable to a variety of data communication standards including 100 Base-X, FDDI and ATM-155.

摘要翻译： 一种用于调谐自适应均衡器以便从传输介质接收数字信号的方法，用于粗调和微调方法以自适应均衡从传输介质接收的信号。 粗调方法调整均衡器，使得后均衡信号开始类似于已知数据模式，例如MLT3数据模式。 粗调方法监视和纠正以下几件事情：非法转换，过均衡，统计数据模式异常和饱和条件。 微调方法与粗调方法和功能从粗调方式停止有效的角度同时运行。 此外，微调方法保持波形锁定。除了均衡器的粗调和微调之外，一个实施例还调整总体信号的增益，使得后均衡信号总是一定幅度。 一个实施例校正了当信号通过接收信道时可能叠加在信号上并且可能导致错误位决定的偏移。 该方法适用于各种数据通信标准，包括100 Base-X，FDDI和ATM-155。