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    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
    41.
    发明授权
    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array 有权
    用于半导体存储器件的晶体管阵列和用于制造垂直沟道晶体管阵列的方法

    公开(公告)号：US07355230B2

    公开(公告)日：2008-04-08

    申请号：US10998975

    申请日：2004-11-30

    申请人： Andreas Thies ,  Klaus Muemmler

    发明人： Andreas Thies ,  Klaus Muemmler

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10885 ,  G11C7/02 ,  G11C7/18 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  Y10S257/905

    摘要： A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

    摘要翻译： 提供了一种用于半导体存储器件的晶体管阵列。 从半导体衬底的本体部分向外延伸的多个半导体柱以行和列布置。 每个柱形成垂直通道存取晶体管的有源区。 绝缘沟槽形成在支柱之间。 掩埋字线沿绝缘沟槽沿支柱排延伸。 位线槽形成在柱柱之间。 位线在位线沟槽的下部垂直于字线延伸。 柱子的第一列和第二列面对每个位线。 每个位线经由由多晶硅形成的单面位线接触件耦合到第一柱柱的支柱中的有源区域，并且与第二柱柱的柱的有源区域绝缘。

    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
    44.
    发明授权
    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array 有权
    用于半导体存储器件的晶体管阵列和用于制造垂直沟道晶体管阵列的方法

    公开(公告)号：US07781773B2

    公开(公告)日：2010-08-24

    申请号：US12042822

    申请日：2008-03-05

    申请人： Andreas Thies ,  Klaus Muemmler

    发明人： Andreas Thies ,  Klaus Muemmler

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10885 ,  G11C7/02 ,  G11C7/18 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  Y10S257/905

    摘要： A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

    摘要翻译： 提供了一种用于半导体存储器件的晶体管阵列。 从半导体衬底的本体部分向外延伸的多个半导体柱以行和列布置。 每个柱形成垂直通道存取晶体管的有源区。 绝缘沟槽形成在支柱之间。 掩埋字线沿绝缘沟槽沿支柱排延伸。 位线槽形成在柱柱之间。 位线在位线沟槽的下部垂直于字线延伸。 柱子的第一列和第二列面对每个位线。 每个位线经由由多晶硅形成的单面位线接触件耦合到第一柱柱的支柱中的有源区域，并且与第二柱柱的柱的有源区域绝缘。

    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
    45.
    发明申请
    Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array 有权
    用于半导体存储器件的晶体管阵列和用于制造垂直沟道晶体管阵列的方法

    公开(公告)号：US20060113587A1

    公开(公告)日：2006-06-01

    申请号：US10998975

    申请日：2004-11-30

    申请人： Andreas Thies ,  Klaus Muemmler

    发明人： Andreas Thies ,  Klaus Muemmler

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/10885 ,  G11C7/02 ,  G11C7/18 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  Y10S257/905

    摘要： A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

    摘要翻译： 提供了一种用于半导体存储器件的晶体管阵列。 从半导体衬底的本体部分向外延伸的多个半导体柱以行和列布置。 每个柱形成垂直通道存取晶体管的有源区。 绝缘沟槽形成在支柱之间。 掩埋字线沿绝缘沟槽沿支柱排延伸。 位线槽形成在柱柱之间。 位线在位线沟槽的下部垂直于字线延伸。 柱子的第一列和第二列面对每个位线。 每个位线经由由多晶硅形成的单面位线接触件耦合到第一柱柱的支柱中的有源区域，并且与第二柱柱的柱的有源区域绝缘。

    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
    46.
    发明申请
    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
    具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法

    公开(公告)号：US20050088895A1

    公开(公告)日：2005-04-28

    申请号：US10897687

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10841 ,  H01L27/10867

    摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

    摘要翻译： 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。

    Method of manufacturing a semiconductor device
    48.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07468306B2

    公开(公告)日：2008-12-23

    申请号：US11139975

    申请日：2005-05-31

    申请人： Andreas Thies ,  Klaus Muemmler

    发明人： Andreas Thies ,  Klaus Muemmler

    IPC分类号： H01L21/20

    CPC分类号： H01L27/0805 ,  H01L28/91

    摘要： A semiconductor substrate is provided comprising a plurality of contact pads arranged on a horizontal surface of the semiconductor substrate. Pillars of a first sacrificial material are formed on the contact pads. A first dielectric layer is deposited thus covering at least said pillars. A first conductive layer is deposited between said pillars covered with the first dielectric layer. The pillars are removed thus providing trenches in the first conductive layer having walls covered with the dielectric layer. A second conductive layer is deposited on the first dielectric layer in the trench. A second dielectric layer is deposited such that at least the second conductive layer in the trench is covered by the second dielectric layer. A third conductive layer is deposited on the second dielectric layer.

    摘要翻译： 提供一种半导体衬底，包括布置在半导体衬底的水平表面上的多个接触焊盘。 在接触垫上形成第一牺牲材料的支柱。 沉积第一介电层，从而覆盖至少所述柱。 在被第一介电层覆盖的柱之间沉积第一导电层。 柱被去除，从而在具有被电介质层覆盖的壁的第一导电层中提供沟槽。 第二导电层沉积在沟槽中的第一介电层上。 沉积第二介电层，使得沟槽中的至少第二导电层被第二介电层覆盖。 第三导电层沉积在第二介电层上。

    Method of manufacturing a semiconductor device
    49.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060267139A1

    公开(公告)日：2006-11-30

    申请号：US11139975

    申请日：2005-05-31

    申请人： Andreas Thies ,  Klaus Muemmler

    发明人： Andreas Thies ,  Klaus Muemmler

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/0805 ,  H01L28/91

    摘要： A semiconductor substrate is provided comprising a plurality of contact pads arranged on a horizontal surface of the semiconductor substrate. Pillars of a first sacrificial material are formed on the contact pads. A first dielectric layer is deposited thus covering at least said pillars. A first conductive layer is deposited between said pillars covered with the first dielectric layer. The pillars are removed thus providing trenches in the first conductive layer having walls covered with the dielectric layer. A second conductive layer is deposited on the first dielectric layer in the trench. A second dielectric layer is deposited such that at least the second conductive layer in the trench is covered by the second dielectric layer. A third conductive layer is deposited on the second dielectric layer.

    摘要翻译： 提供一种半导体衬底，包括布置在半导体衬底的水平表面上的多个接触焊盘。 在接触垫上形成第一牺牲材料的支柱。 沉积第一介电层，从而覆盖至少所述柱。 在被第一介电层覆盖的柱之间沉积第一导电层。 柱被去除，从而在具有被电介质层覆盖的壁的第一导电层中提供沟槽。 第二导电层沉积在沟槽中的第一介电层上。 沉积第二介电层，使得沟槽中的至少第二导电层被第二介电层覆盖。 第三导电层沉积在第二介电层上。