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    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
    1.
    发明申请
    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
    具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法

    公开(公告)号：US20050088895A1

    公开(公告)日：2005-04-28

    申请号：US10897687

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10841 ,  H01L27/10867

    摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

    摘要翻译： 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    2.
    发明授权
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US07141845B2

    公开(公告)日：2006-11-28

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    3.
    发明申请
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US20050083724A1

    公开(公告)日：2005-04-21

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

    Dram cell pair and dram memory cell array
    4.
    发明授权
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US07301192B2

    公开(公告)日：2007-11-27

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    Dram cell pair and dram memory cell array
    5.
    发明申请
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US20060076602A1

    公开(公告)日：2006-04-13

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L29/94 ,  H01L21/8244

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    Lighting device
    9.
    发明授权
    Lighting device 有权
    照明设备

    公开(公告)号：US09016918B2

    公开(公告)日：2015-04-28

    申请号：US13262812

    申请日：2010-03-30

    申请人： Wolfgang Mueller

    发明人： Wolfgang Mueller

    IPC分类号： F21V7/04 ,  B60Q3/00 ,  B60Q3/02 ,  F21V8/00 ,  B60Q1/26

    CPC分类号： B60Q3/64 ,  B60Q1/263 ,  B60Q3/745 ,  G02B6/0021 ,  G02B6/0073 ,  G02B6/0095

    摘要： A lighting device is disclosed that is configured for mounting in or on a motor vehicle. The lighting device comprises a light guiding element and a light source. The light guiding element has a light entry face and a light exit face. A depth of the lighting device perpendicular to the light exit face corresponds essentially fully to the depth of the light guiding element.

    摘要翻译： 公开了一种被配置为安装在机动车辆中或机动车辆上的照明装置。 照明装置包括导光元件和光源。 导光元件具有光入射面和光出射面。 垂直于光出射面的照明装置的深度基本上完全对准导光元件的深度。

    LIGHTING DEVICE FOR A VEHICLE INTERIOR
    10.
    发明申请
    LIGHTING DEVICE FOR A VEHICLE INTERIOR 审中-公开
    车内照明装置

    公开(公告)号：US20140286029A1

    公开(公告)日：2014-09-25

    申请号：US14119476

    申请日：2012-05-24

    申请人： Wolfgang Mueller

    发明人： Wolfgang Mueller

    IPC分类号： F21S8/10

    CPC分类号： B60Q3/82 ,  B60Q3/225 ,  B60Q3/64 ,  B60Q3/745

    摘要： The invention relates to a lighting device (1) for a vehicle interior, comprising a light guide element (4) having a light coupling surface and a light decoupling surface, wherein a luminous flux can be introduced into the light coupling surface by means of at least one light source, wherein the light guide element (4) is retained at least in some sections in a frame element (2) at the edges thereof. According to the invention, the at least one light source is arranged in the frame element (2) in such a way that the light decoupling surface (13) extends substantially perpendicularly to the light coupling surface, wherein the light guide element (4) is structured at least in some sections.

    摘要翻译： 本发明涉及一种用于车辆内部的照明装置（1），其包括具有光耦合表面和光去耦表面的导光元件（4），其中光通量可以通过在光耦合表面 至少一个光源，其中所述光导元件（4）至少在其边缘处被保持在框架元件（2）中的一些部分中。 根据本发明，至少一个光源被布置在框架元件（2）中，使得光去耦表面（13）基本上垂直于光耦合表面延伸，其中导光元件（4）是 至少在某些部分结构化。