公开(公告)号：US08918745B2

公开(公告)日：2014-12-23

申请号：US13803048

申请日：2013-03-14

申请人： Lynn Wang ,  Sriram Madhavan ,  Luigi Capodieci

发明人： Lynn Wang ,  Sriram Madhavan ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/70 ,  G03F7/70466 ,  G03F7/70475

摘要： Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

摘要翻译： 公开了能够降低布局的两个互补曝光掩模和/或窗口之间的密度差的方法，以及用于执行该方法的装置。 实施例包括：确定具有要由第一和第二掩模解决的特征的IC设计的层; 通过将第一组特征的第一密度与第二组特征的第二密度进行比较来确定密度差; 确定要由第一掩模解析的第一特征的层上的区域; 以及基于所述密度差在所述区域内插入由所述第二掩模求解的多边形。

公开(公告)号：US20140215415A1

公开(公告)日：2014-07-31

申请号：US13755374

申请日：2013-01-31

申请人： Lynn WANG ,  Vito Dai ,  Luigi Capodieci

发明人： Lynn WANG ,  Vito Dai ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5081 ,  Y02T10/82

摘要： A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

摘要翻译： 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括扫描绘制的半导体设计布局以基于与预先表征的难以制造的图案的匹配来确定所绘制的半导体设计布局内的难以制造的图案，基于预定的相关性来确定校正的图案 在校正图案和预先表征的难以制造图案之间，并且在所绘制的半导体设计布局内用修正图案代替难以制造的图案。

公开(公告)号：US08516407B1

公开(公告)日：2013-08-20

申请号：US13361595

申请日：2012-01-30

申请人： Lynn T. Wang ,  Sriram Madhavan ,  Luigi Capodieci

发明人： Lynn T. Wang ,  Sriram Madhavan ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/70

摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

摘要翻译： 公开了一种用于制造集成电路的方法，其包括根据实施例，为集成电路提供双重图案化技术兼容的逻辑设计，所述逻辑设计包括多个元件; 对所述多个元素中的一个或多个元素的设计进行评分以产生设计得分; 至少部分基于设计得分修改设计; 生成实现修改后的逻辑设计的掩码集; 并采用掩模组来实现半导体衬底中的逻辑设计。

公开(公告)号：US08103979B2

公开(公告)日：2012-01-24

申请号：US12254172

申请日：2008-10-20

申请人： Yi Zou ,  Luigi Capodieci

发明人： Yi Zou ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

摘要翻译： 使用反光刻法创建集成电路设计布局的最佳辅助特征规则集。 全芯片布局被光刻仿真，并确定了可印刷性故障区域。 对特征布局图案进行特征分析，并对独特特征布局进行反光刻以形成辅助特征。 分析所得到的辅助特征布局以创建辅助特征规则集。 然后可以将规则应用于利用集成电路设计布局图案化的光掩模，以打印最佳辅助特征。 所得到的光掩模可用于在半导体衬底上形成集成电路。

公开(公告)号：US07799517B1

公开(公告)日：2010-09-21

申请号：US10930432

申请日：2004-08-31

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G21K5/10 ,  G03C5/04

CPC分类号： G03F7/70466 ,  G03F7/70125 ,  G03F7/70283 ,  G03F7/70425

摘要： A method of forming a feature on a device is disclosed. A photo resist layer is formed over the device and a dipole illuminator having a pole orientation axis in a first direction is used to expose a first geometrical pattern onto the resist layer. The first geometrical pattern is substantially oriented in the same direction as the pole orientation axis of the dipole illuminator. A dipole illuminator having a pole orientation axis substantially orthogonal to the first direction then is used to expose a second geometrical pattern onto the resist layer. The second geometrical pattern is oriented substantially orthogonal to the first direction.

摘要翻译： 公开了一种在设备上形成特征的方法。 在该器件上形成光致抗蚀剂层，并且使用具有第一方向的极取向轴的偶极照明器将第一几何图案暴露在抗蚀剂层上。 第一几何图案基本上定向在与偶极照明器的极取向轴相同的方向上。 使用具有与第一方向基本正交的极取向轴的偶极照明器，以将第二几何图案暴露在抗蚀剂层上。 第二几何图案基本上与第一方向正交。

公开(公告)号：US07757190B2

公开(公告)日：2010-07-13

申请号：US11613006

申请日：2006-12-19

申请人： Vito Dai ,  Jie Yang ,  Norma Rodriguez ,  Luigi Capodieci

发明人： Vito Dai ,  Jie Yang ,  Norma Rodriguez ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.

摘要翻译： 当他们具有超过标准限制所需的特定参数时，布局模式被识别为有问题的。 有问题的布局模式与DRC-Plus面板中的首选设计规则相关联。 扫描布局数据以生成任何有问题的布局模式的匹配位置。 匹配位置被转发到DRC引擎，其将匹配位置的布局参数与DRC-Plus卡板中的相应优选布局规则进行比较。 DRC-Plus检查结果用于修改布局以提高布局的可制造性。

公开(公告)号：US20090144686A1

公开(公告)日：2009-06-04

申请号：US11948218

申请日：2007-11-30

申请人： KEVIN R. LENSING ,  Jason P. Cain ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

发明人： KEVIN R. LENSING ,  Jason P. Cain ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

IPC分类号： G06F19/00

CPC分类号： G06F17/5081

摘要： A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.

摘要翻译： 一种方法包括根据多个布局设计规则生成用于集成电路设备的布局。 识别与布局设计规则的至少一个子集相关联的布局上的多个计量站点。 生成与每个测量点相关联的度量标签。 基于计量标签生成至少一个用于确定集成电路装置的特性的计量配方。 使用至少一个计量学方法收集计量学数据。 基于测量数据修改至少一个子集中的选定的布局设计规则。

公开(公告)号：US07543256B1

公开(公告)日：2009-06-02

申请号：US10790590

申请日：2004-03-01

申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

IPC分类号： G06F17/50

CPC分类号： G06F8/48 ,  G06F8/447 ,  G06F17/5022

摘要： A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

摘要翻译： 一种方法包括提供初始的IC器件设计，该设计具有期望的一组电特性。 生成对应于初始设备设计的布局表示。 仿真工具用于确定布局表示是否对应于具有所需电气特性的IC器件设计。 此外，使用仿真工具评估由于工艺变化而设计的IC器件内的结构之间的变化。 该变体可用于确定设计是否被优化。

公开(公告)号：US20080148211A1

公开(公告)日：2008-06-19

申请号：US11613006

申请日：2006-12-19

申请人： Vito Dai ,  Jie Yang ,  Norma Rodriguez ,  Luigi Capodieci

发明人： Vito Dai ,  Jie Yang ,  Norma Rodriguez ,  Luigi Capodieci

IPC分类号： G06F9/455

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.

摘要翻译： 当他们具有超过标准限制所需的特定参数时，布局模式被识别为有问题的。 有问题的布局模式与DRC-Plus面板中的首选设计规则相关联。 扫描布局数据以生成任何有问题的布局模式的匹配位置。 匹配位置被转发到DRC引擎，其将匹配位置的布局参数与DRC-Plus卡板中的相应优选布局规则进行比较。 DRC-Plus检查结果用于修改布局以提高布局的可制造性。

公开(公告)号：US07354682B1

公开(公告)日：2008-04-08

申请号：US10887640

申请日：2004-07-09

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G03F1/00 ,  G03F1/14

CPC分类号： G03F1/34 ,  G03F1/28 ,  G03F1/36

摘要： A chromeless phase-shift mask (CPM) for imaging sub-100 nm contact holes and a method of making the same are disclosed. The CPM includes a plurality of features formed on a substrate and a plurality of suppressors formed on the substrate. Light energy passing through the plurality of suppressors substantially reduces an interference generated by light energy passing through features within an optical proximity of each other, thereby significantly improving contrast and depth of focus. The plurality of features can be formed in a grid pattern, and the suppressors can be formed in adjacent corners of each feature. The size and location of the suppressors can be varied with respect to the features to obtain a desired image.

摘要翻译： 公开了一种用于成像次100nm接触孔的无色相移掩模（CPM）及其制造方法。 CPM包括形成在基板上的多个特征和形成在基板上的多个抑制器。 通过多个抑制器的光能基本上减少了通过彼此光学接近的特征的光能产生的干扰，从而显着地改善了对比度和聚焦深度。 多个特征可以形成为网格图案，并且抑制器可以形成在每个特征的相邻角部。 抑制器的尺寸和位置可以相对于特征而变化以获得期望的图像。