Multilayer package substrate with stress buffer

    公开(公告)号:US11784113B2

    公开(公告)日:2023-10-10

    申请号:US17233110

    申请日:2021-04-16

    Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

    ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCE

    公开(公告)号:US20230055211A1

    公开(公告)日:2023-02-23

    申请号:US17406150

    申请日:2021-08-19

    Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

    ANTENNA-ON-PACKAGE INCLUDING MULTIPLE TYPES OF ANTENNA

    公开(公告)号:US20210328367A1

    公开(公告)日:2021-10-21

    申请号:US17232849

    申请日:2021-04-16

    Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including ≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

    Package substrate having integrated passive device(s) between leads

    公开(公告)号:US12218036B2

    公开(公告)日:2025-02-04

    申请号:US18177273

    申请日:2023-03-02

    Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

    Semiconductor package with shunt and patterned metal trace

    公开(公告)号:US12211800B2

    公开(公告)日:2025-01-28

    申请号:US17500086

    申请日:2021-10-13

    Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

    Antenna-on-package including multiple types of antenna

    公开(公告)号:US12113293B2

    公开(公告)日:2024-10-08

    申请号:US18169682

    申请日:2023-02-15

    CPC classification number: H01Q23/00 H01L23/66 H01Q1/2283

    Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

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