中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.019 seconds)

    PACKAGED SEMICONDUCTOR DEVICE
    2.
    发明申请
    PACKAGED SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200066716A1

    公开(公告)日：2020-02-27

    申请号：US16667051

    申请日：2019-10-29

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

    IPC: H01L27/07 ,  H01L23/31 ,  H05K1/02 ,  H01L23/00 ,  H01L23/522

    Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

    Multiple underfills for flip chip packages
    4.
    发明授权
    Multiple underfills for flip chip packages 有权

    公开(公告)号：US11217460B2

    公开(公告)日：2022-01-04

    申请号：US15975167

    申请日：2018-05-09

    Applicant: Texas Instruments Incorporated

    Inventor： Makarand Ramkrishna Kulkarni ,  Tae Kim

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

    Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.

    Stacked die multichip module package
    5.
    发明授权
    Stacked die multichip module package 有权

    公开(公告)号：US11081472B2

    公开(公告)日：2021-08-03

    申请号：US16574226

    申请日：2019-09-18

    Applicant: Texas Instruments Incorporated

    Inventor： Jonathan Almeria Noquil ,  Makarand Ramkrishna Kulkarni

    IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.

    Semiconductor package with shunt and patterned metal trace
    6.
    发明授权
    Semiconductor package with shunt and patterned metal trace 有权

    公开(公告)号：US12211800B2

    公开(公告)日：2025-01-28

    申请号：US17500086

    申请日：2021-10-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538

    Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

Patent Agency Ranking