公开(公告)号：US12243849B2

公开(公告)日：2025-03-04

申请号：US17491378

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chittranjan Mohan Gupta ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Jie Chen ,  Tianyi Luo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

公开(公告)号：US20240072025A1

公开(公告)日：2024-02-29

申请号：US17893312

申请日：2022-08-23

Applicant: Texas Instruments Incorporated

Inventor： Rajen M. Murugan ,  Yiqi Tang ,  Jie Chen ,  Ramlah Abdul Razak

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48195 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/17787 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025

Abstract: An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.

公开(公告)号：US20240006267A1

公开(公告)日：2024-01-04

申请号：US17809808

申请日：2022-06-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/4882 ,  H01L24/16

Abstract: An example semiconductor package comprises a ceramic header having a top surface and a cavity formed within the ceramic header. The cavity is open at the top surface. A semiconductor die is mounted within the cavity of the ceramic header. A lid structure is coupled to the top surface of the ceramic header. The lid structure and ceramic header form a portion of a package enclosing the semiconductor die. One or more silver tubes are in contact with a first surface of the semiconductor die and with a first surface of the lid structure. A seal ring is located between the top surface of the ceramic header and the lid structure. The seal ring couples the lid structure to the ceramic header. The one or more silver tubes are hollow and filled with a getter material.

公开(公告)号：US20210175195A1

公开(公告)日：2021-06-10

申请号：US17028353

申请日：2020-09-22

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yong Xie ,  Rajen Manicon Murugan ,  Woochan Kim

IPC: H01L23/00 ,  H01L25/16

Abstract: In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.

公开(公告)号：US12165989B2

公开(公告)日：2024-12-10

申请号：US18295192

申请日：2023-04-03

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20240178155A1

公开(公告)日：2024-05-30

申请号：US18071972

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Chittranjan Mohan Gupta ,  Rajen Manicon Murugan ,  Jie Chen

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4839 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/3025

Abstract: An electronic device includes a multilevel package substrate having a first level, a second level, a third level, a conductive signal trace that extends in the second level, and a conductive box shield that surrounds a portion of the conductive signal trace. The electronic device includes a semiconductor die attached to the multilevel package substrate and having a conductive structure coupled to an end of the conductive signal trace. The electronic device includes a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US10892405B2

公开(公告)日：2021-01-12

申请号：US16404978

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US10262957B2

公开(公告)日：2019-04-16

申请号：US15949746

申请日：2018-04-10

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Minhong Mi ,  Gary Paul Morrison ,  Jie Chen ,  Kenneth Robert Rhyner ,  Stanley Craig Beddingfield ,  Chittranjan Mohan Gupta ,  Django Earl Trombley

IPC: H01Q1/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q23/00 ,  H05K1/02 ,  H01Q1/32 ,  H05K1/18

Abstract: An integrated circuit (IC) package includes an IC die and a wave channel that electrically couples the IC die to a solder ball array. The wave channel is configured to resonate at an operating frequency band of the IC die.

公开(公告)号：US12191259B2

公开(公告)日：2025-01-07

申请号：US17569724

申请日：2022-01-06

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495 ,  H01L25/00 ,  H01L25/18 ,  H03K17/042

Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

公开(公告)号：US20240178154A1

公开(公告)日：2024-05-30

申请号：US18070708

申请日：2022-11-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen ,  Jaimal Mallory Williamson

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a molded package structure, where the multilevel package substrate has opposite first and second substrate sides, first and second conductive pads spaced apart from one another along the first substrate side, and a conductive substrate terminal that is exposed along the second substrate side and is electrically coupled to the second conductive pad. The semiconductor die is attached to the first substrate side and has opposite first and second die sides, and a die terminal along the first die side, the die terminal electrically coupled to the first conductive pad. The molded has a package side, a metal shield along the package side, and a conductive package via that extends through the molded package structure and electrically couples the metal shield to the second conductive pad.