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66 条记录 (耗时 0.027 秒)

    Semiconductor device and operation method thereof
    41.
    发明申请
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号：US20090115467A1

    公开(公告)日：2009-05-07

    申请号：US12005515

    申请日：2007-12-27

    申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    IPC分类号： H03B19/00 ,  G06F1/06

    CPC分类号： G06F1/06

    摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

    摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

    Semiconductor device and operation method thereof
    42.
    发明申请
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号：US20090115459A1

    公开(公告)日：2009-05-07

    申请号：US12005564

    申请日：2007-12-27

    申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    IPC分类号： H03K3/017 ,  H03K5/125

    CPC分类号： H03K5/1565

    摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

    摘要翻译： 一种半导体器件，包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号 半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

    Filtering circuit, phase identity determination circuit and delay locked loop
    43.
    发明授权
    Filtering circuit, phase identity determination circuit and delay locked loop 有权
    滤波电路，相位识别确定电路和延迟锁定环

    公开(公告)号：US08664987B2

    公开(公告)日：2014-03-04

    申请号：US13607234

    申请日：2012-09-07

    申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

    IPC分类号： H03K5/00

    CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/235

    摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

    摘要翻译： 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为对输入信号进行滤波并生成滤波的 信号与操作时钟同步。

    Semiconductor device and operation method thereof for generating phase clock signals
    45.
    发明授权
    Semiconductor device and operation method thereof for generating phase clock signals 失效
    用于产生相位时钟信号的半导体器件及其操作方法

    公开(公告)号：US08283962B2

    公开(公告)日：2012-10-09

    申请号：US12005515

    申请日：2007-12-27

    申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    IPC分类号： H03K3/00

    CPC分类号： G06F1/06

    摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

    摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

    Semiconductor memory device having data clock training circuit
    46.
    发明授权
    Semiconductor memory device having data clock training circuit 有权
    具有数据时钟训练电路的半导体存储器件

    公开(公告)号：US08130890B2

    公开(公告)日：2012-03-06

    申请号：US12005492

    申请日：2007-12-27

    申请人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

    发明人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

    IPC分类号： H04L7/02 ,  H04L7/04

    CPC分类号： G11C29/02 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

    摘要： A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

    摘要翻译： 数据时钟分频器电路包括训练解码器和分频器。 响应于模式寄存器组的命令和地址，训练解码器输出表示时钟对准训练的开始的时钟对准训练信号。 响应于训练解码器的输出复位的分频器接收内部数据时钟以将内部数据时钟的频率分成两半。 数据时钟分频器电路确保足够的操作余量，使得数据时钟和系统时钟在预设的时钟训练操作时间内对齐，通过复位数据时钟以对应于时钟训练操作开始的定时，由此 为高速系统提供时钟训练。

    Injection locking clock generator and clock synchronization circuit using the same
    47.
    发明授权
    Injection locking clock generator and clock synchronization circuit using the same 失效
    注入锁定时钟发生器和时钟同步电路使用相同

    公开(公告)号：US07952438B2

    公开(公告)日：2011-05-31

    申请号：US12217049

    申请日：2008-06-30

    申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

    发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

    IPC分类号： H03B27/01

    CPC分类号： H03L7/0812 ,  H03L7/18 ,  H03L7/24

    摘要： An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

    摘要翻译： 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。

    Semiconductor memory device
    48.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07948814B2

    公开(公告)日：2011-05-24

    申请号：US12164797

    申请日：2008-06-30

    申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

    摘要： A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

    摘要翻译： 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

    Semiconductor device and operation method thereof
    49.
    发明授权
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号：US07863955B2

    公开(公告)日：2011-01-04

    申请号：US12005564

    申请日：2007-12-27

    申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

    摘要翻译： 一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

    Counter with overflow prevention capability
    50.
    发明授权
    Counter with overflow prevention capability 失效
    具有防溢出功能的计数器

    公开(公告)号：US07738621B2

    公开(公告)日：2010-06-15

    申请号：US12005933

    申请日：2007-12-28

    申请人： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

    发明人： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

    IPC分类号： G06M3/00 ,  H03K21/40

    CPC分类号： G06M3/12

    摘要： A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

    摘要翻译： 具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码 值，但其前一值不是最大值。