Semiconductor device and operation method thereof for generating phase clock signals
    1.
    发明授权
    Semiconductor device and operation method thereof for generating phase clock signals 失效
    用于产生相位时钟信号的半导体器件及其操作方法

    公开(公告)号:US08283962B2

    公开(公告)日:2012-10-09

    申请号:US12005515

    申请日:2007-12-27

    IPC分类号: H03K3/00

    CPC分类号: G06F1/06

    摘要: A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

    摘要翻译: 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗,该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的,以便具有 低频和不同的激活时序具有恒定的相位差。

    Semiconductor device and operation method thereof
    2.
    发明授权
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号:US07863955B2

    公开(公告)日:2011-01-04

    申请号:US12005564

    申请日:2007-12-27

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565

    摘要: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

    摘要翻译: 一种半导体器件包括:脉冲信号产生单元,用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元,用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元,用于响应于使能信号检测外部时钟信号的占空比。

    Counter with overflow prevention capability
    3.
    发明授权
    Counter with overflow prevention capability 失效
    具有防溢出功能的计数器

    公开(公告)号:US07738621B2

    公开(公告)日:2010-06-15

    申请号:US12005933

    申请日:2007-12-28

    IPC分类号: G06M3/00 H03K21/40

    CPC分类号: G06M3/12

    摘要: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

    摘要翻译: 具有防溢能力的计数器包括:计数单元,被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元,被配置为当输出代码的当前值为最大值时,控制计数单元停止计数输出代码 值,但其前一值不是最大值。

    Low pass filter and lock detector circuit
    4.
    发明授权
    Low pass filter and lock detector circuit 有权
    低通滤波器和锁定检测电路

    公开(公告)号:US07876148B2

    公开(公告)日:2011-01-25

    申请号:US12344552

    申请日:2008-12-28

    IPC分类号: H03L7/093 H03L7/095

    摘要: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

    摘要翻译: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元,被配置为对驱动器单元的输出电压进行充电的充电/放电单元,被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元,被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

    Clock synchronization circuit and operation method thereof
    5.
    发明授权
    Clock synchronization circuit and operation method thereof 失效
    时钟同步电路及其操作方法

    公开(公告)号:US07855933B2

    公开(公告)日:2010-12-21

    申请号:US12165045

    申请日:2008-06-30

    IPC分类号: G11C8/00

    摘要: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

    摘要翻译: 一种具有时钟同步电路的半导体存储器件,其能够执行期望的相位/频率锁定操作,而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环,其检测反馈时钟信号和参考时钟信号之间的相位/频率差,以产生对应于检测到的相位/频率差的振荡控制电压信号,并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率,并产生与参考时钟信号同步的内部时钟信号。

    Bias voltage generation circuit and clock synchronizing circuit
    6.
    发明授权
    Bias voltage generation circuit and clock synchronizing circuit 有权
    偏置电压发生电路和时钟同步电路

    公开(公告)号:US07812650B2

    公开(公告)日:2010-10-12

    申请号:US12157235

    申请日:2008-06-09

    IPC分类号: H03L7/06

    摘要: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

    摘要翻译: 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元,被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

    BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT
    7.
    发明申请
    BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT 有权
    偏置电压发生电路和时钟同步电路

    公开(公告)号:US20090160510A1

    公开(公告)日:2009-06-25

    申请号:US12157235

    申请日:2008-06-09

    IPC分类号: H03L7/06 H03K3/01

    摘要: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

    摘要翻译: 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元,被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

    Semiconductor device and operation method thereof
    8.
    发明申请
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号:US20090115467A1

    公开(公告)日:2009-05-07

    申请号:US12005515

    申请日:2007-12-27

    IPC分类号: H03B19/00 G06F1/06

    CPC分类号: G06F1/06

    摘要: A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

    摘要翻译: 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗,该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的,以便具有 低频和不同的激活时序具有恒定的相位差。

    Semiconductor device and operation method thereof
    9.
    发明申请
    Semiconductor device and operation method thereof 失效
    半导体装置及其动作方法

    公开(公告)号:US20090115459A1

    公开(公告)日:2009-05-07

    申请号:US12005564

    申请日:2007-12-27

    IPC分类号: H03K3/017 H03K5/125

    CPC分类号: H03K5/1565

    摘要: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

    摘要翻译: 一种半导体器件,包括:脉冲信号产生单元,用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元,用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号 半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

    LOW PASS FILTER AND LOCK DETECTOR CIRCUIT
    10.
    发明申请
    LOW PASS FILTER AND LOCK DETECTOR CIRCUIT 有权
    低通滤波器和锁定检测电路

    公开(公告)号:US20090168944A1

    公开(公告)日:2009-07-02

    申请号:US12344552

    申请日:2008-12-28

    IPC分类号: H03D3/24

    摘要: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

    摘要翻译: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元,被配置为对驱动器单元的输出电压进行充电的充电/放电单元,被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元,被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。