公开(公告)号：US11450628B2

公开(公告)日：2022-09-20

申请号：US16846416

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chia-Chia Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L49/02 ,  H01L23/48 ,  H01L21/56

Abstract: Provided is a package structure including a first die; a plurality of through vias, aside the first die; a first encapsulant laterally encapsulating the first die and the plurality of through vias; a first redistribution layer (RDL) structure on first sides of the first die, plurality of through vias, and the first encapsulant; a second RDL structure on second sides of the first die, the plurality of through vias, and the first encapsulant; and a plurality of conductive connectors, electrically connected to the second RDL structure. Portions of the first RDL structure, the plurality of through vias, and the second RDL structure are electrically connected to each other and form a solenoid inductor laterally aside the first die.

公开(公告)号：US11424197B2

公开(公告)日：2022-08-23

申请号：US16421497

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/552

Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.

公开(公告)号：US20220223530A1

公开(公告)日：2022-07-14

申请号：US17229322

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US11335767B2

公开(公告)日：2022-05-17

申请号：US15710847

申请日：2017-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang ,  Tzu-Chun Tang ,  Wei-Ting Chen ,  Chieh-Yen Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L25/00 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/64 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.

公开(公告)号：US11302649B2

公开(公告)日：2022-04-12

申请号：US16908284

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu ,  Chih-Yuan Chang

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L23/50 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

公开(公告)号：US11211371B2

公开(公告)日：2021-12-28

申请号：US16882191

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/498 ,  H01L23/48 ,  H01L25/16 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

Abstract: In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.

公开(公告)号：US11171088B2

公开(公告)日：2021-11-09

申请号：US16221632

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Che-Wei Hsu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/66 ,  H01Q1/22 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

公开(公告)号：US11139206B2

公开(公告)日：2021-10-05

申请号：US16676778

申请日：2019-11-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/552 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure passing through the substrate. The semiconductor device structure includes a conductive shielding structure passing through the substrate and surrounding the first insulating layer. The semiconductor device structure includes a second insulating layer passing through the substrate and surrounding the conductive shielding structure. The semiconductor device structure includes a second conductive structure passing through the substrate. The semiconductor device structure includes a third insulating layer passing through the substrate and surrounding the second conductive structure. The semiconductor device structure includes a conductive layer passing through the first insulating layer.

公开(公告)号：US11094682B2

公开(公告)日：2021-08-17

申请号：US16744194

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rabiul Islam ,  Chuei-Tang Wang ,  Stefan Rusu ,  Weiwei Song

IPC: H01L23/31 ,  H01L21/56 ,  G02B6/12 ,  H01L25/16 ,  H01L23/367 ,  H01L23/00

Abstract: A package structure includes a package component, a stacked die package, a plurality of optical fibers and a heat spreading structure. The stacked die package is disposed on and electrically connected to the package component. The stacked die package includes a first semiconductor die and a plurality of second semiconductor dies. The first semiconductor die has a plurality of first bonding elements. The second semiconductor dies are disposed on the first semiconductor die and have a plurality of second bonding elements, wherein the plurality of first bonding elements and the plurality of second bonding elements are facing one another and bonded together through hybrid bonding. The plurality of optical fibers is attached to the plurality of second semiconductor dies of the stacked die package. The heat spreading structure is disposed on the package component and surrounding the stacked die package.

公开(公告)号：US20210225824A1

公开(公告)日：2021-07-22

申请号：US16744194

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rabiul Islam ,  Chuei-Tang Wang ,  Stefan Rusu ,  Weiwei Song

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  G02B6/12

Abstract: A package structure includes a package component, a stacked die package, a plurality of optical fibers and a heat spreading structure. The stacked die package is disposed on and electrically connected to the package component. The stacked die package includes a first semiconductor die and a plurality of second semiconductor dies. The first semiconductor die has a plurality of first bonding elements. The second semiconductor dies are disposed on the first semiconductor die and have a plurality of second bonding elements, wherein the plurality of first bonding elements and the plurality of second bonding elements are facing one another and bonded together through hybrid bonding. The plurality of optical fibers is attached to the plurality of second semiconductor dies of the stacked die package. The heat spreading structure is disposed on the package component and surrounding the stacked die package.