公开(公告)号：US11495503B2

公开(公告)日：2022-11-08

申请号：US17373303

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

公开(公告)号：US11211116B2

公开(公告)日：2021-12-28

申请号：US16922270

申请日：2020-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

公开(公告)号：US20210343601A1

公开(公告)日：2021-11-04

申请号：US17373303

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

公开(公告)号：US20210305262A1

公开(公告)日：2021-09-30

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  G11C11/418

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US11127746B2

公开(公告)日：2021-09-21

申请号：US16529380

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Chia-Hao Pao ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L29/76 ,  H01L27/088 ,  H01L23/48 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44 ,  H01L27/11 ,  H01L23/535 ,  H01L23/528 ,  H01L27/108 ,  H01L23/522

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.

公开(公告)号：US11062963B2

公开(公告)日：2021-07-13

申请号：US16521870

申请日：2019-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.

公开(公告)号：US20210124863A1

公开(公告)日：2021-04-29

申请号：US16796900

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ruey-Wen Chang ,  Feng-Ming Chang

IPC: G06F30/392 ,  G06F30/3323

Abstract: A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.

公开(公告)号：US10977409B1

公开(公告)日：2021-04-13

申请号：US16796900

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ruey-Wen Chang ,  Feng-Ming Chang

IPC: G06F30/3323 ,  G06F30/392 ,  H01L27/02 ,  H01L29/786 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092

Abstract: A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.

公开(公告)号：US20210098469A1

公开(公告)日：2021-04-01

申请号：US16984983

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC: H01L27/11

Abstract: An integrated circuit device includes a FinFET disposed over a doped region of a first type dopant, wherein the FinFET includes a first fin structure and first source/drain (S/D) features, the first fin structure having a first width; and a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes a second fin structure and second S/D features, the second fin structure having a second width that is larger than the first width, wherein the fin-based well strap connects the doped region to a voltage.

公开(公告)号：US20210098058A1

公开(公告)日：2021-04-01

申请号：US16922270

申请日：2020-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.