公开(公告)号：US20220238484A1

公开(公告)日：2022-07-28

申请号：US17214043

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/544

Abstract: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.

公开(公告)号：US20220223564A1

公开(公告)日：2022-07-14

申请号：US17314713

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/544 ,  H01L21/768 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

公开(公告)号：US11380653B2

公开(公告)日：2022-07-05

申请号：US16903370

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

Abstract: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.

公开(公告)号：US11380598B2

公开(公告)日：2022-07-05

申请号：US17008966

申请日：2020-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/28 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00

Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.

公开(公告)号：US11309243B2

公开(公告)日：2022-04-19

申请号：US16929118

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.

公开(公告)号：US20220077117A1

公开(公告)日：2022-03-10

申请号：US17455767

申请日：2021-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31 ,  H01L23/485 ,  H01L23/00 ,  H01L25/00

Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.

公开(公告)号：US11257791B2

公开(公告)日：2022-02-22

申请号：US16876108

申请日：2020-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L23/00

Abstract: A stacked die structure includes a base die, a top die and conductive terminals electrically connected to the top die. The base die includes a base semiconductor substrate, a base interconnection layer disposed on the base semiconductor substrate, and a base bonding layer disposed on the base interconnection layer. The top die is stacked on the base die and electrically connected to the base die, wherein the top die includes a top bonding layer, a top semiconductor substrate, a top interconnection layer, top conductive pads and top grounding vias. The top bonding layer is hybrid bonded to the base bonding layer. The top interconnection layer is disposed on the top semiconductor substrate and includes a dielectric layer, conductive layers embedded in the dielectric layer, and conductive vias joining the conductive layers. The conductive pads and top grounding vias are embedded in the dielectric layer and disposed on the conductive layers.

公开(公告)号：US11239225B2

公开(公告)日：2022-02-01

申请号：US16515003

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/00 ,  H01L21/02 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00

Abstract: Three-dimensional integrated circuit structures and methods of forming the same are disclosed. One of the three-dimensional integrated circuit structures includes a first die, a plurality of second dies and a dielectric structure. The second dies are bonded to the first die. The dielectric structure is disposed between the second dies. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom are in contact with the second dielectric layer and form a first angle. A second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom.

公开(公告)号：US20210391322A1

公开(公告)日：2021-12-16

申请号：US16900996

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L27/06 ,  H01L23/538 ,  H01L21/78 ,  H01L21/768

Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.

公开(公告)号：US20210375819A1

公开(公告)日：2021-12-02

申请号：US17074107

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.