公开(公告)号：US11923302B2

公开(公告)日：2024-03-05

申请号：US17854683

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/08135 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

公开(公告)号：US20220367322A1

公开(公告)日：2022-11-17

申请号：US17815515

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

公开(公告)号：US11342297B2

公开(公告)日：2022-05-24

申请号：US16877512

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Jie Chen ,  Sen-Bor Jan ,  Sung-Feng Yeh

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.

公开(公告)号：US11335656B2

公开(公告)日：2022-05-17

申请号：US17027175

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ching-Pin Yuan ,  Sung-Feng Yeh ,  Sen-Bor Jan ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

公开(公告)号：US20210118827A1

公开(公告)日：2021-04-22

申请号：US16655244

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sen-Bor Jan ,  Chih-Chia Hu

IPC: H01L23/64 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.

公开(公告)号：US20210098409A1

公开(公告)日：2021-04-01

申请号：US16877512

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Jie Chen ,  Sen-Bor Jan ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.

公开(公告)号：US12223252B2

公开(公告)日：2025-02-11

申请号：US18171072

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheng-Hung Yeh ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Yi-Kan Cheng ,  Hsiu-Chuan Shu

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20240105619A1

公开(公告)日：2024-03-28

申请号：US18523553

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/08135 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

公开(公告)号：US20240021544A1

公开(公告)日：2024-01-18

申请号：US18358343

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Chun-Chiang Kuo ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/0649 ,  H01L24/09 ,  H01L24/83 ,  H01L24/03 ,  H01L24/33 ,  H01L25/50 ,  H01L24/80 ,  H01L25/0657 ,  H01L23/562 ,  H01L2225/06568 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2224/94

Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

公开(公告)号：US11855029B2

公开(公告)日：2023-12-26

申请号：US17837492

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu ,  Sen-Bor Jan

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/784 ,  H01L23/538 ,  H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L24/16 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/566 ,  H01L23/3114 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00

Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.